Commit 47cd00fa authored by wdenk's avatar wdenk

* Patches by Robert Schwebel, 06 Mar 2003:

  - fix bug in BOOTP code (must use NetCopyIP)
  - update of CSB226 port
  - clear BSS segment on XScale
  - added support for i2c_init_board() function
  - update to the Innokom plattform

* Extend support for redundand environments for configurations where
  environment size < sector size
parent db2f721f
......@@ -2,6 +2,16 @@
Changes since U-Boot 0.2.2:
======================================================================
* Patches by Robert Schwebel, 06 Mar 2003:
- fix bug in BOOTP code (must use NetCopyIP)
- update of CSB226 port
- clear BSS segment on XScale
- added support for i2c_init_board() function
- update to the Innokom plattform
* Extend support for redundand environments for configurations where
environment size < sector size
* Patch by Rune Torgersen, 13 Feb 2003:
Add support for Motorola MPC8266ADS board
......
......@@ -897,6 +897,17 @@ The following options need to be configured:
controls the rate of data transfer. The data rate thus
is 1 / (I2C_DELAY * 4).
CFG_I2C_INIT_BOARD
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
in progress. On some boards it is possible to access
the i2c SCLK line directly, either by using the
processor pin as a GPIO or by having a second pin
connected to the bus. If this option is defined a
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
......@@ -1043,7 +1054,7 @@ The following options need to be configured:
If CONFIG_ENV_OVERWRITE is #defined in your config
file, the write protection for vendor parameters is
completely disabled. Anybody can change or delte
completely disabled. Anybody can change or delete
these parameters.
Alternatively, if you #define _both_ CONFIG_ETHADDR
......
......@@ -47,7 +47,9 @@ SECTIONS
armboot_end_data = .;
. = ALIGN(4);
bss_start = .;
.bss : { *(.bss) }
bss_end = .;
armboot_end = .;
}
......@@ -32,10 +32,30 @@
# define SHOW_BOOT_PROGRESS(arg)
#endif
/*
* Miscelaneous platform dependent initialisations
/**
* misc_init_r: - misc initialisation routines
*/
int misc_init_r(void)
{
uchar *str;
/* determine if the software update key is pressed during startup */
#if 0
/* not ported yet... */
if (GPLR0 & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
printf("using bootcmd_update (sw-update button pressed)\n");
str = getenv("bootcmd_update");
}
setenv("bootcmd",str);
#endif
return 0;
}
/**
* board_init: - setup some data structures
......
This diff is collapsed.
......@@ -313,16 +313,22 @@ mem_init:
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* There should 9 writes, since the first write doesn't */
/* trigger a refresh cycle on PXA250. See Intel PXA250 and */
/* PXA210 Processors Specification Update, */
/* Jan 2003, Errata #116, page 30. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
......@@ -339,7 +345,6 @@ mem_init:
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
......@@ -378,10 +383,11 @@ initclks:
str r2, [r1]
/* enable the 32Khz oscillator for RTC and PowerManager */
/*
ldr r1, =OSCC
mov r2, #OSCC_OON
str r2, [r1]
*/
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
......@@ -404,8 +410,7 @@ initclks:
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
#ifndef DEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
......@@ -415,7 +420,6 @@ initclks:
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
......
......@@ -47,7 +47,9 @@ SECTIONS
armboot_end_data = .;
. = ALIGN(4);
bss_start = .;
.bss : { *(.bss) }
bss_end = .;
armboot_end = .;
}
......@@ -31,12 +31,228 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
#define FLASH_BANK_SIZE 0x02000000
#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
#if defined CFG_JFFS_CUSTOM_PART
#include <jffs2/jffs2.h>
#endif
/* Debugging macros ------------------------------------------------------ */
#undef FLASH_DEBUG
//#define FLASH_DEBUG 1
/* Some debug macros */
#if (FLASH_DEBUG > 2 )
#define PRINTK3(args...) printf(args)
#else
#define PRINTK3(args...)
#endif
#if FLASH_DEBUG > 1
#define PRINTK2(args...) printf(args)
#else
#define PRINTK2(args...)
#endif
#ifdef FLASH_DEBUG
#define PRINTK(args...) printf(args)
#else
#define PRINTK(args...)
#endif
/* ------------------------------------------------------------------------ */
/* Development system: we have only 16 MB Flash */
#ifdef CONFIG_MTD_INNOKOM_16MB
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */
#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
#endif
/* Production system: we have 64 MB Flash */
#ifdef CONFIG_MTD_INNOKOM_64MB
#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */
#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#if defined CFG_JFFS_CUSTOM_PART
/**
* jffs2_part_info - get information about a JFFS2 partition
*
* @part_num: number of the partition you want to get info about
* @return: struct part_info* in case of success, 0 if failure
*/
static struct part_info part;
#ifdef CONFIG_MTD_INNOKOM_16MB
#ifdef CONFIG_MTD_INNOKOM_64MB
#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
#endif
struct part_info* jffs2_part_info(int part_num) {
PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
/* u-boot partition */
if(part_num==0){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00000000;
part.size=256*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* primary OS+firmware partition */
if(part_num==1){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00040000;
part.size=768*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* secondary OS+firmware partition */
if(part_num==2){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00100000;
part.size=8*1024*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* data partition */
if(part_num==3){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00900000;
part.size=7*1024*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
PRINTK("jffs2_part_info: end of partition table\n");
return 0;
}
#endif /* CONFIG_MTD_INNOKOM_16MB */
#ifdef CONFIG_MTD_INNOKOM_64MB
#ifdef CONFIG_MTD_INNOKOM_16MB
#error Please define only one CONFIG_MTD_INNOKOM_XXMB option.
#endif
struct part_info* jffs2_part_info(int part_num) {
PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
/* u-boot partition */
if(part_num==0){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00000000;
part.size=256*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* primary OS+firmware partition */
if(part_num==1){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x00040000;
part.size=16*1024*1024-128*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* secondary OS+firmware partition */
if(part_num==2){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x01020000;
part.size=16*1024*1024-128*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
/* data partition */
if(part_num==3){
if(part.usr_priv==(void*)1) return &part;
memset(&part, 0, sizeof(part));
part.offset=(char*)0x02000000;
part.size=32*1024*1024;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
return &part;
}
PRINTK("jffs2_part_info: end of partition table\n");
return 0;
}
#endif /* CONFIG_MTD_INNOKOM_64MB */
#endif /* defined CFG_JFFS_CUSTOM_PART */
/**
* flash_init: - initialize data structures for flash chips
*
......@@ -71,10 +287,10 @@ ulong flash_init(void)
size += flash_info[i].size;
}
/* Protect monitor and environment sectors */
/* Protect u-boot sectors */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
CFG_FLASH_BASE + (256*1024) - 1,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
......@@ -178,32 +394,38 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
printf("Erasing sector %2d ... ", sect);
PRINTK("\n");
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
if (info->protect[sect] == 0) { /* not protected */
u32 * volatile addr = (u32 * volatile)(info->start[sect]);
u16 * volatile addr = (u16 * volatile)(info->start[sect]);
/* erase sector: */
/* The strata flashs are aligned side by side on */
/* the data bus, so we have to write the commands */
/* to both chips here: */
PRINTK("unlocking sector\n");
*addr = 0x0060;
*addr = 0x00d0;
*addr = 0x00ff;
*addr = 0x00200020; /* erase setup */
*addr = 0x00D000D0; /* erase confirm */
PRINTK("erasing sector\n");
*addr = 0x0020;
PRINTK("confirming erase\n");
*addr = 0x00D0;
while ((*addr & 0x00800080) != 0x00800080) {
while ((*addr & 0x0080) != 0x0080) {
PRINTK(".");
if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase*/
*addr = 0x00FF00FF; /* read mode */
*addr = 0x00B0; /* suspend erase*/
*addr = 0x00FF; /* read mode */
rc = ERR_TIMOUT;
goto outahere;
}
}
*addr = 0x00500050; /* clear status register cmd. */
*addr = 0x00FF00FF; /* resest to read mode */
PRINTK("clearing status register\n");
*addr = 0x0050;
PRINTK("resetting to read mode");
*addr = 0x00FF;
}
printf("ok.\n");
......@@ -233,7 +455,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
static int write_word (flash_info_t *info, ulong dest, ushort data)
{
ushort *addr = (ushort *)dest, val;
volatile u16 *addr = (u16 *)dest, val;
int rc = ERR_OK;
int flag;
......
......@@ -25,6 +25,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
......@@ -32,10 +33,53 @@
# define SHOW_BOOT_PROGRESS(arg)
#endif
/*
* Miscelaneous platform dependent initialisations
/**
* i2c_init_board - reset i2c bus. When the board is powercycled during a
* bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
* The Innokom board has GPIO70 connected to SCLK which can be toggled
* until all chips think that their current cycles are finished.
*/
int i2c_init_board(void)
{
int i;
/* set gpio pin to output */
GPDR(70) |= GPIO_bit(70);
for (i = 0; i < 11; i++) {
GPCR(70) = GPIO_bit(70);
udelay(10);
GPSR(70) = GPIO_bit(70);
udelay(10);
}
/* set gpio pin to input */
GPDR(70) &= ~GPIO_bit(70);
return 0;
}
/**
* misc_init_r: - misc initialisation routines
*/
int misc_init_r(void)
{
uchar *str;
/* determine if the software update key is pressed during startup */
if (GPLR0 & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
printf("using bootcmd_update (sw-update button pressed)\n");
str = getenv("bootcmd_update");
}
setenv("bootcmd",str);
return 0;
}
/**
* board_init: - setup some data structures
......@@ -51,7 +95,7 @@ int board_init (void)
/* so we do _nothing_ here */
/* arch number of Innokom board */
gd->bd->bi_arch_number = 258;
gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
......
......@@ -38,6 +38,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
sub pc,pc,#4
.endm
_TEXT_BASE:
.word TEXT_BASE
/*
* Memory setup
......@@ -222,6 +225,12 @@ mem_init:
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
/* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
adr r3, mem_init /* r0 <- current position of code */
ldr r2, =mem_init
cmp r3, r2 /* skip init if in place */
beq initirqs
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
......@@ -313,17 +322,23 @@ mem_init:
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* There should 9 writes, since the first write doesn't */
/* trigger a refresh cycle on PXA250. See Intel PXA250 and */
/* PXA210 Processors Specification Update, */
/* Jan 2003, Errata #116, page 30. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
......@@ -339,7 +354,6 @@ mem_init:
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
......@@ -405,8 +419,7 @@ initclks:
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
#ifndef DEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
......@@ -416,7 +429,6 @@ initclks:
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
......
......@@ -47,7 +47,9 @@ SECTIONS
armboot_end_data = .;
. = ALIGN(4);
bss_start = .;
.bss : { *(.bss) }
bss_end = .;
armboot_end = .;
}
......@@ -47,7 +47,9 @@ SECTIONS
armboot_end_data = .;
. = ALIGN(4);
bss_start = .;
.bss : { *(.bss) }
bss_end = .;
armboot_end = .;
}
......@@ -301,7 +301,7 @@ extern char *stdio_names[];
void show_stdio_dev(void)
{
/* Print informations */
/* Print information */
printf ("In: ");
if (stdio_devices[stdin] == NULL) {
printf ("No input devices available!\n");
......
......@@ -38,7 +38,7 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_generic/string.o (.text)
. = env_offset;
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
......
......@@ -496,7 +496,7 @@ int console_init_r (void)
}
#ifndef CFG_CONSOLE_INFO_QUIET
/* Print informations */
/* Print information */
printf ("In: ");
if (stdio_devices[stdin] == NULL) {
printf ("No input devices available!\n");
......
......@@ -34,6 +34,7 @@
#include <environment.h>
#include <cmd_nvedit.h>
#include <linux/stddef.h>
#include <malloc.h>
#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
#define CMD_SAVEENV
......@@ -41,11 +42,6 @@
#error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH
#endif
#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) && \
defined(CFG_ENV_ADDR_REDUND)
#error CFG_ENV_ADDR_REDUND should not be used when CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
#endif
#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE)
#error CFG_ENV_SIZE_REDUND should not be less then CFG_ENV_SIZE
#endif
......@@ -80,8 +76,9 @@ static env_t *flash_addr = (env_t *)CFG_ENV_ADDR;
#ifdef CFG_ENV_ADDR_REDUND
static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR_REDUND;
static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SIZE - 1;
static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1;
/* CFG_ENV_ADDR is supposed to be on sector boundary */
static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1;
static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1;
static uchar active_flag = 1;
static uchar obsolete_flag = 0;
......@@ -164,6 +161,8 @@ int env_init(void)
int saveenv(void)
{
int rc = 1;
ulong up_data = 0;
char *saved_data = NULL;
debug ("Protect off %08lX ... %08lX\n",
(ulong)flash_addr, end_addr);
......@@ -179,6 +178,22 @@ int saveenv(void)
goto Done;
}
#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
up_data = (end_addr_new + 1 - ((long)flash_addr_new + CFG_ENV_SIZE));
debug ("Data to save 0x%x\n", up_data);
if (up_data) {
if ((saved_data = malloc(up_data)) == NULL) {
printf("Unable to save the rest of sector (%ld)\n",
up_data);
goto Done;
}
memcpy(saved_data,
(void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data);
debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n",
(long)flash_addr_new + CFG_ENV_SIZE,
up_data, saved_data);
}
#endif
puts ("Erasing Flash...");
debug (" %08lX ... %08lX ...",
(ulong)flash_addr_new, end_addr_new);
......@@ -212,6 +227,18 @@ int saveenv(void)
}
puts ("done\n");
#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
if (up_data) { /* restore the rest of sector */
debug ("Restoring the rest of data to 0x%x len 0x%x\n",
(long)flash_addr_new + CFG_ENV_SIZE, up_data);
if (flash_write(saved_data,
(long)flash_addr_new + CFG_ENV_SIZE,
up_data)) {
flash_perror(rc);
goto Done;
}
}
#endif
{
env_t * etmp = flash_addr;
ulong ltmp = end_addr;
......@@ -226,6 +253,8 @@ int saveenv(void)
rc = 0;