Commit 4c902345 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Tom Rini

lpc32xx: fix calculation of HCLK PLL output clock

Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
Signed-off-by: default avatarVladimir Zapolskiy <>
parent f0aa26f0
......@@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void)
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
fout = fref * m_div;
fcco = fout;
fcco = fref * m_div;
fout = fcco;
fcco *= p_div;
do_div(fout, p_div);
} else
fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment