Commit 4ef218f6 authored by Wolfgang Denk's avatar Wolfgang Denk

Coding style cleanup; update CHANGELOG.

Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
parent bf6a9ca9
This diff is collapsed.
......@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
......@@ -54,8 +54,6 @@ const unsigned char fpgadata[] =
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
#include "../common/auto_update.h"
#ifdef CONFIG_CPCI405AB
......@@ -88,13 +86,11 @@ au_image_t au_image[] = {
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */
int cpci405_version(void);
int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f (void)
{
#ifndef CONFIG_CPCI405_VER2
......@@ -113,10 +109,10 @@ int board_early_init_f (void)
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
......@@ -178,51 +174,48 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
#else
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/* ------------------------------------------------------------------------- */
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
return 0; /* no, board is cpci405 */
return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
return 0; /* no, board is cpci405 */
return 0; /* no, board is cpci405 */
else
return -1; /* yes, board is cterm-m2 */
return -1; /* yes, board is cterm-m2 */
#endif
}
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
return -1; /* yes, board is cpci405 host */
return -1; /* yes, board is cpci405 host */
else
return 0; /* no, board is cpci405 adapter */
return 0; /* no, board is cpci405 adapter */
}
int cpci405_version(void)
{
unsigned long cntrl0Reg;
......@@ -235,8 +228,8 @@ int cpci405_version(void)
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
udelay(1000); /* wait some time before reading input */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
......@@ -262,13 +255,11 @@ int cpci405_version(void)
}
}
int misc_init_f (void)
{
return 0; /* dummy implementation */
}
int misc_init_r (void)
{
unsigned long cntrl0Reg;
......@@ -432,7 +423,6 @@ int misc_init_r (void)
return (0);
}
/*
* Check Board Identity:
*/
......@@ -488,7 +478,7 @@ int checkboard (void)
}
#ifndef CONFIG_CPCI405_VER2
puts ("\nFPGA: ");
puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
......@@ -515,7 +505,6 @@ long int initdram (int board_type)
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
......@@ -527,7 +516,6 @@ void reset_phy(void)
#endif
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_CPCI405_VER2
......@@ -550,7 +538,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */
#if defined(CONFIG_PCI)
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
......@@ -585,14 +572,13 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_CPCI405AB
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|= CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
&= ~CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
& CFG_FPGA_MODE_1WIRE)
/*
......@@ -615,7 +601,6 @@ int OWTouchReset(void)
return result;
}
/*
* Send 1 a 1-wire write bit.
* Provide 10us recovery time.
......@@ -641,7 +626,6 @@ void OWWriteBit(int bit)
}
}
/*
* Read a bit from the 1-wire bus and return it.
* Provide 10us recovery time.
......@@ -661,7 +645,6 @@ int OWReadBit(void)
return result;
}
void OWWriteByte(int data)
{
int loop;
......@@ -672,7 +655,6 @@ void OWWriteByte(int data)
}
}
int OWReadByte(void)
{
int loop, result = 0;
......@@ -687,7 +669,6 @@ int OWReadByte(void)
return result;
}
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned short val;
......@@ -728,7 +709,6 @@ U_BOOT_CMD(
NULL
);
#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
......
......@@ -197,14 +197,13 @@ void load_sernum_ethaddr (void)
* - The checksum, stored in the last 2 Bytes, is correct
*/
if ((strncmp (buf,"ATR",3) != 0) ||
((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1]))
{
((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
/* EEprom is not programmed */
printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
} else {
/* get the MACs */
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
buf[3],
buf[4],
buf[5],
......@@ -212,7 +211,7 @@ void load_sernum_ethaddr (void)
buf[7],
buf[8]);
setenv ("ethaddr", (char *) mac);
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
buf[9],
buf[10],
buf[11],
......@@ -378,7 +377,7 @@ static int pcs440ep_sha1 (int docheck)
org[i] = ptroff[i];
ptroff[i] = 0;
}
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
if (docheck == 2) {
......@@ -796,7 +795,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
unsigned char output[20];
int len;
int i;
data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
len = simple_strtoul (argv[2], NULL, 16);
sha1_csum (data, len, (unsigned char *)output);
......@@ -823,7 +822,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} else {
rcode = pcs440ep_sha1 (0);
}
return rcode;
return rcode;
}
return rcode;
}
......@@ -861,4 +860,3 @@ void ide_set_reset (int idereset)
udelay (10000);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
......@@ -1222,7 +1222,7 @@ mck_return:
*/
#ifdef CONFIG_440
.globl dcache_disable
.globl icache_disable
.globl icache_disable
.globl icache_enable
dcache_disable:
icache_disable:
......
......@@ -480,9 +480,9 @@
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x0000)
/* This addresses need to be shifted one place to the left
/* These addresses need to be shifted one place to the left
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
* This values are shifted
* These values are shifted
*/
#define CFG_ATA_PORT_ADDR(port) ((port) << 1)
......
......@@ -17,7 +17,7 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
* MA 02110-1301 USA
*/
/*
* The SHA-1 standard was published by NIST in 1993.
......@@ -35,76 +35,76 @@ extern "C" {
#define SHA1_SUM_LEN 20
/**
* \brief SHA-1 context structure
* \brief SHA-1 context structure
*/
typedef struct
{
unsigned long total[2]; /*!< number of bytes processed */
unsigned long state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
unsigned long total[2]; /*!< number of bytes processed */
unsigned long state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
}
sha1_context;
/**
* \brief SHA-1 context setup
* \brief SHA-1 context setup
*
* \param ctx SHA-1 context to be initialized
* \param ctx SHA-1 context to be initialized
*/
void sha1_starts( sha1_context *ctx );
/**
* \brief SHA-1 process buffer
* \brief SHA-1 process buffer
*
* \param ctx SHA-1 context
* \param ctx SHA-1 context
* \param input buffer holding the data
* \param ilen length of the input data
* \param ilen length of the input data
*/
void sha1_update( sha1_context *ctx, unsigned char *input, int ilen );
/**
* \brief SHA-1 final digest
* \brief SHA-1 final digest
*
* \param ctx SHA-1 context
* \param ctx SHA-1 context
* \param output SHA-1 checksum result
*/
void sha1_finish( sha1_context *ctx, unsigned char output[20] );
/**
* \brief Output = SHA-1( input buffer )
* \brief Output = SHA-1( input buffer )
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param ilen length of the input data
* \param output SHA-1 checksum result
*/
void sha1_csum( unsigned char *input, int ilen,
unsigned char output[20] );
unsigned char output[20] );
/**
* \brief Output = SHA-1( file contents )
* \brief Output = SHA-1( file contents )
*
* \param path input file name
* \param path input file name
* \param output SHA-1 checksum result
* \return 0 if successful, or 1 if fopen failed
* \return 0 if successful, or 1 if fopen failed
*/
int sha1_file( char *path, unsigned char output[20] );
/**
* \brief Output = HMAC-SHA-1( input buffer, hmac key )
* \brief Output = HMAC-SHA-1( input buffer, hmac key )
*
* \param key HMAC secret key
* \param key HMAC secret key
* \param keylen length of the HMAC key
* \param input buffer holding the data
* \param ilen length of the input data
* \param ilen length of the input data
* \param output HMAC-SHA-1 result
*/
void sha1_hmac( unsigned char *key, int keylen,
unsigned char *input, int ilen,
unsigned char output[20] );
unsigned char *input, int ilen,
unsigned char output[20] );
/**
* \brief Checkup routine
* \brief Checkup routine
*
* \return 0 if successful, or 1 if the test failed
* \return 0 if successful, or 1 if the test failed
*/
int sha1_self_test( void );
......
This diff is collapsed.
......@@ -438,7 +438,7 @@ cache_post_test6_reloc:
blr
/* Test instructions.
*/
*/
cache_post_test_inst:
li r3, 0
li r3, -1
......
......@@ -37,7 +37,7 @@ int fpu_status(void)
{
if (mfspr(ccr0) & CCR0_DAPUIB)
return 0; /* Disabled */
else
else
return 1; /* Enabled */
}
......
......@@ -43,12 +43,11 @@
#include <asm/processor.h>
static struct
{
int number;
char * name;
unsigned long mask;
unsigned long value;
static struct {
int number;
char * name;
unsigned long mask;
unsigned long value;
} spr_test_list [] = {
/* Standard Special-Purpose Registers */
......@@ -65,7 +64,7 @@ static struct
{0x11f, "PVR", 0x00000000, 0x00000000},
/* Additional Special-Purpose Registers.
* The values must match the initialization
* The values must match the initialization
* values from cpu/ppc4xx/start.S
*/
{0x30, "PID", 0x00000000, 0x00000000},
......
......@@ -84,7 +84,7 @@ int main (int argc, char **argv)
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
/* create a copy, so we can blank out the sha1 sum */
data = malloc (len);
memcpy (data, ptr, len);
......@@ -93,12 +93,11 @@ int main (int argc, char **argv)
for (i = 0; i < SHA1_SUM_LEN; i++) {
ptroff[i] = 0;
}
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
printf ("U-Boot sum:\n");
for (i = 0; i < 20 ; i++)
{
for (i = 0; i < 20 ; i++) {
printf ("%02X ", output[i]);
}
printf ("\n");
......@@ -109,7 +108,7 @@ int main (int argc, char **argv)
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
free (data);
(void) munmap((void *)ptr, len);
(void) close (ifd);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment