Commit 4f2532c4 authored by York Sun's avatar York Sun

armv8/ls2085a_emu: Enable sync of refresh

Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent 1478fdef
......@@ -20,4 +20,5 @@
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
#define CONFIG_FSL_DDR_SYNC_REFRESH
#endif /* __LS2_EMU_H */
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