Commit 4fb3925f authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: remove RPXClassic, RPXlite boards support

Enough time has passed since these boards were moved to Orphan. Remove.

 - Remove board/RPXlite/*
 - Remove board/RPXClassic/*
 - Remove include/configs/RPXlite.h
 - Remove include/configs/RPXClassic.h
 - Clean-up defined(CONFIG_RPXCLASSIC)
 - Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
parent aa6e1e45
......@@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_RPXCLASSIC) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
......@@ -207,10 +206,6 @@ void cpu_init_f (volatile immap_t * immr)
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
#ifdef CONFIG_RPXCLASSIC
rpxclassic_init ();
#endif
#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
rpxlite_init ();
#endif
......
......@@ -461,11 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
#ifdef CONFIG_RPXCLASSIC
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif
#ifdef CONFIG_RPXLITE
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
......@@ -512,8 +507,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
#elif defined(CONFIG_RPXCLASSIC)
udelay (100000); /* wait 100 ms */
#endif
return 1;
......
......@@ -182,7 +182,7 @@ static int smc_init (void)
#endif
#endif /* CONFIG_FADS */
#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
#if defined(CONFIG_RPXLITE)
/* Enable Monitor Port Transceiver */
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
#endif /* CONFIG_RPXLITE */
......
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = RPXClassic.o flash.o eccx.o
# Porting U-Boot onto RPXClassic LF_BW31 board
# Written by Pierre AUBERT
# E-Mail p.aubert@staubli.com
# Stäubli Faverges - <www.staubli.com>
#
# Sept. 20 2001
#
# Cross compile: Montavista Hardhat ported on HP-UX 10.20
#
Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000
DRAM : 16 Mb from 0
NVRAM : 512 kb from 0xfa000000
- environment is stored in NVRAM
- Mac address is read from EEPROM
- ethernet on SCC1 or fast ethernet on FEC are running (depending on the
configuration flag CONFIG_FEC_ENET)
/*
* (C) Copyright 2001
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
* U-Boot port on RPXClassic LF (CLLF_BW31) board
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <config.h>
#include <mpc8xx.h>
#include <net.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
static unsigned char aschex_to_byte (unsigned char *cp);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
0x0CFFCC00, 0x33FFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
*/
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: RPXClassic\n");
return (0);
}
/*-----------------------------------------------------------------------------
* board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
*-----------------------------------------------------------------------------
*/
static void board_get_enetaddr(uchar *enet)
{
int i;
char buff[256], *cp;
/* Initialize I2C */
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
i2c_read (0x54, 0, 1, (uchar *)buff, 128);
i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
/* Retrieve MAC address in buffer (key EA) */
for (cp = buff;;) {
if (cp[0] == 'E' && cp[1] == 'A') {
cp += 3;
/* Read MAC address */
for (i = 0; i < 6; i++, cp += 2) {
enet[i] = aschex_to_byte ((unsigned char *)cp);
}
}
/* Scan to the end of the record */
while ((*cp != '\n') && (*cp != (char)0xff)) {
cp++;
}
/* If the next character is a \n, 0 or ff, we are done. */
cp++;
if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
break;
}
#ifdef CONFIG_FEC_ENET
/* The MAC address is the same as normal ethernet except the 3rd byte */
/* (See the E.P. Planet Core Overview manual */
enet[3] |= 0x80;
#endif
printf("MAC address = %pM\n", enet);
}
int misc_init_r(void)
{
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
board_get_enetaddr(enetaddr);
eth_setenv_enetaddr("ethaddr", enetaddr);
}
return 0;
}
void rpxclassic_init (void)
{
/* Enable NVRAM */
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
#ifdef CONFIG_FEC_ENET
/* Validate the fast ethernet tranceiver */
*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
#endif
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
*/
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
return (get_ram_size(base, maxsize));
}
/*-----------------------------------------------------------------------------
* aschex_to_byte --
*-----------------------------------------------------------------------------
*/
static unsigned char aschex_to_byte (unsigned char *cp)
{
u_char byte, c;
c = *cp++;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte = c * 16;
c = *cp;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte += c;
return (byte);
}
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/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = RPXlite.o flash.o
This diff is collapsed.
After several heart-struck failure, I got one workable way to program
each other in FLASH between PlanetCore and U-Boot.
Hardware Platform : RPXlite DW(EP 823 H1 DW)
1. From U-Boot to PlanetCore
Utilities : PlanetCore Boot Loader - PCL200.mot
[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot
PCL200.mot pcl200.bin
[Target Operation]
u-boot>t 100000 pcl200.bin
u-boot>go 0x100000
## Starting application at 0x00100000 ...
MPC8xx PlanetCore Flash Burner v2.00
Copyright 2001 Embedded Planet. All rights reserved.
Construct Flash Device.....done.
Program MPC8xx PlanetCore Boot Loader v2.00
Built Sep 19, 2001 at 14:34:42
Image located from FC000000 to FC01B5D1.
(Skipping an image, only loading low boot image)
Low boot board detected, skipping high boot image.
Erasing, programming and verifying will start in 20
seconds
Press P to start immediately or ESC to cancel
Press Space or Enter for more options.
..............
Erasing
Programming
FLASH programmed successfully!
Press R to induce a hard reset
MPC8xx PlanetCore Boot Loader v2.00
Copyright 2001 Embedded Planet. All rights reserved.
DRAM available size = 64 MB
wvCV
DRAM OK
>
2. From PlanetCore to U-Boot
Utilities : PlanetCore FLASH Burner - PCB200.mot
Use Flash Burner to finish the work:
First, TFTP the U-Boot image file to RAM; For example,
RPXlite_DW.bin to 0x400000
Second, TFTP FLASH Burner to RAM; For example,
0x100000
Third, run the FLASH Burner and Program the U-Boot
image into the correct location in FLASH.
[Target Operation]
MPC8xx PlanetCore Boot Loader v2.00
Copyright 2001 Embedded Planet. All rights reserved.
DRAM available size = 64 MB
wvCV
DRAM OK
>t
Load using tftp via Ethernet
Enter server IP address <172.16.115.6> :
Enter server filename <PCL200.mot> : RPXlite_DW.bin
Enter (B)inary or (S)record input mode <S> : B
Enter address offset : <00400000 hex> :
Total bytes = 120096 in 232184 uSecs
Loaded addresses 00400000 through 0041D51F.
Start address = 00400000
>t
Load using tftp via Ethernet
Enter server IP address <172.16.115.6> :
Enter server filename <RPXlite_DW.bin> : PCB200.mot
Enter (B)inary or (S)record input mode <B> : S
Enter address offset : <00000000 hex> :
.512.1024..2048....4096.....
Total bytes = 326280 in 2570249 uSecs
Loaded addresses 00100000 through 0011BB51.
Start address = 00100000
>go
[Go 00100000]
MPC8xx PlanetCore Flash Burner v2.00
Copyright 2001 Embedded Planet. All rights reserved.
Construct Flash Device.....done.
Bad start address
Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length =
0xFFFFFFFF
Forcing Menu Interface
h[elp] Show commands.
c[ode] Show information on code to be loaded.
di[splay] Display all flash sections.
du[mp] Dump memory. d ? for more info.
e[rase] Erase flash sections.
f[ill] Fill flash sections.
im[age] Toggle load high, low, or both flash
images.
in[fo] Show flash information.
ma[p] Show memory map.
mo[dify] Modify memory. m ? for more info.
p[rogram] Erase, program, and verify now.
reset Restart the loader.
s[how] Show flash sections to erase and program.
t[est] Test flash sections.
q[uit] Quit without programming.
#program 400000 ff000000 1D51F
doProgram( 400000 ff000000 1D51F )
Start = 0x00400000, target = 0xFF000000, length =
0x0001D51F
Erasing sector 0xFF000000, length 0x008000.
Erasing sector 0xFF008000, length 0x008000.
Erasing sector 0xFF010000, length 0x008000.
Erasing sector 0xFF018000, length 0x008000.
Programming FF000000 through FF01D51E
FLASH programmed successfully!
Press R to induce a hard reset
Forcing Hard Reset by MachineCheck and
ResetOnCheckstop...
U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB
D-Cache
Board: RPXlite_DW
DRAM: 64 MB
FLASH: 16 MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
u-boot>
-------------------------------------------------
Well, sometimes network function of PlanetCore couldn't work when
switching from U-Boot to PlanetCore. For example, you couldn't
download a file from HOST PC via TFTP. Don't worry, just restart your
HOST PC and everything would work as smooth as clockwork. I don't
know the reason WHY:-)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Merry Christmas and Happy New Year!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
=====
Best regards,
Sam
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*
* DRAM related UPMA register values are modified.
* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
*/
#include <common.h>