Commit 5043045d authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: ppc4xx: remove korat board support

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>
parent 41eb4e5c
......@@ -13,9 +13,6 @@ config TARGET_CSB272
config TARGET_CSB472
bool "Support csb472"
config TARGET_KORAT
bool "Support korat"
config TARGET_LWMON5
bool "Support lwmon5"
select SUPPORT_SPL
......@@ -195,7 +192,6 @@ source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
source "board/korat/Kconfig"
source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
......
if TARGET_KORAT
config SYS_BOARD
default "korat"
config SYS_CONFIG_NAME
default "korat"
endif
KORAT BOARD
M: Larry Johnson <lrj@acm.org>
S: Maintained
F: board/korat/
F: include/configs/korat.h
F: configs/korat_defconfig
F: configs/korat_perm_defconfig
#
# (C) Copyright 2002-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = korat.o
extra-y += init.o
The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
Bank #1 (with the starting address depending on the flash size detected at
runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
cannot be modified in the field. This also prevents FLASH0 from executing
commands to return chip information, so its configuration is hard-coded in
U-Boot.
There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
0xF7FDFFFF are used for the redundant copy of the parameters. These locations
are used by both versions of U-Boot.
On booting, the permanent U-Boot in FLASH0 begins executing. After performing
minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
the switch is sensed as open before a timeout period, then U-Boot branches to
address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
beginning. If the switch remains closed thoughout the timeout period, the
permanent U-Boot activates the on-board buzzer until the switch is sensed as
opened. It then continues to execute without branching to FLASH1. The effect
of this is that normally the Korat board boots its upgradable U-Boot, but, if
this has been corrupted, the user can boot the permanent U-Boot, which can then
be used to erase and reload FLASH1 as needed.
Note that it is not necessary for the permanent U-Boot to have all the latest
features, but only that it have sufficient functionality (working "tftp",
"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
The build sequence:
make korat_perm_config
make all
builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
make korat_config
make all
creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
2008-02-22, Larry Johnson <lrj@acm.org>
The CompactFlash(R) controller on the Korat board provides a hi-speed USB
interface. This may be connected to either a dedicated port on the on-board
USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
environment variable "korat_usbcf" can be used to specify which of these two
USB host ports is used for CompactFlash. The valid setting for the variable are
the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
PowerPC USB port is used. In all other cases the on-board USB controller is
used, but if "korat_usbcf" is defined but is set to a string other than the two
valid options, a warning is also issued.
2009-01-28, Larry Johnson <lrj@acm.org>
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# Korat (PPC440EPx) board
#
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(emul),1)
PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
endif
ifndef CONFIG_KORAT_PERMANENT
LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
endif
/*
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
/*
* TLB entries for SDRAM are not needed on this platform. They are
* generated dynamically in the SPD DDR2 detection routine.
*/
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
/* TLB-entry for EBC */
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
/* TLB-entry for Internal Registers & OCM */
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
/*TLB-entry PCI registers*/
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
/* TLB-entry PCI IO Space - from sr@denx.de */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
tlbtab_end
#if defined(CONFIG_KORAT_PERMANENT)
.globl korat_branch_absolute
korat_branch_absolute:
mtlr r3
blr
#endif
This diff is collapsed.
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xF7FBFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xF7FBF000 :
{
arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_KORAT=y
CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT"
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_KORAT=y
......@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
......
This diff is collapsed.
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