Commit 506f0441 authored by wdenk's avatar wdenk

Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:

- fix SRAM and SDRAM memory sizing
- add status LED support
- add MAC address for second (SCC1) ethernet port

Update default environment for TQM8260 board
parent cdd8a0f1
......@@ -2,6 +2,13 @@
Changes since U-Boot 0.2.2:
======================================================================
* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
- fix SRAM and SDRAM memory sizing
- add status LED support
- add MAC address for second (SCC1) ethernet port
* Update default environment for TQM8260 board
* Patch by Rick Bronson, 16 Mar 2003:
- Add NAND flash support for reading, writing, and erasing NAND
flash (certain forms of which are called SmartMedia).
......
......@@ -28,6 +28,9 @@
#include <net.h> /* for eth_init() */
#include <rtc.h>
#include "sixnet.h"
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
#endif
#define ORMASK(size) ((-size) & OR_AM_MSK)
......@@ -35,6 +38,22 @@ static long ram_size(ulong *, long);
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress (int status)
{
#if defined(CONFIG_STATUS_LED)
# if defined(STATUS_LED_BOOT)
if (status == 15) {
/* ready to transfer to kernel, make sure LED is proper state */
status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
}
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}
#endif
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
* returns 0 if recognized, -1 if unknown
......@@ -235,6 +254,9 @@ int misc_init_r (void)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
char* s;
char* e;
int reg;
bd_t *bd = gd->bd;
memctl->memc_or2 = NVRAM_OR_PRELIM;
......@@ -283,18 +305,19 @@ int misc_init_r (void)
immap->im_sit.sit_rtc = tim;
}
#if 0
/* The code below is no longer valid since the prototype of
* eth_init() and eth_halt() have been changed to support
* multi-ethernet feature in U-Boot; the eth_initialize()
* routine should be called before any access to the ethernet
* callbacks.
/* set up ethernet address for SCC ethernet. If eth1addr
* is present it gets a unique address, otherwise it
* shares the FEC address.
*/
s = getenv("eth1addr");
if (s == NULL)
s = getenv("ethaddr");
for (reg=0; reg<6; ++reg) {
bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e+1 : e;
}
/* FIXME - for now init ethernet to force PHY special mode */
eth_init(bd);
eth_halt();
#endif
return (0);
}
......@@ -307,7 +330,7 @@ int misc_init_r (void)
*
* The memory size MUST be a power of 2 for this to work.
*
* The only memory modified is 4 bytes at offset 0. This is important
* The only memory modified is 8 bytes at offset 0. This is important
* since for the SRAM this location is reserved for autosizing, so if
* it is modified and the board is reset before ram_size() completes
* no damage is done. Normally even the memory at 0 is preserved. The
......@@ -319,28 +342,27 @@ static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
volatile long *base_addr = base;
volatile long *flash = (volatile long*)CFG_FLASH_BASE;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong junk;
ulong save2; /* to make test non-destructive */
long ramsize = -1; /* size not determined yet */
save = *base_addr; /* save value at 0 so can restore */
save2 = *(base_addr+1); /* save value at 4 so can restore */
/* is any SRAM present? */
*base_addr = 0x5555aaaa;
/* use flash read to modify data bus, since with no SRAM present
* the data bus may retain the value if our code is running
* completely in the cache.
/* It is important to drive the data bus with different data so
* it doesn't remember the value and look like RAM that isn't there.
*/
junk = *flash;
*(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
if (*base_addr != 0x5555aaaa)
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
junk = *flash; /* use flash read to modify data bus */
*(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
......@@ -355,6 +377,7 @@ static long ram_size(ulong *base, long maxsize)
}
*base_addr = save; /* restore value at 0 */
*(base_addr+1) = save2; /* restore value at 4 */
return (ramsize);
}
......@@ -426,18 +449,21 @@ const uint sdram_table[] =
MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
/* MAMR values work in either mamr or mbmr */
/* 8 column SDRAM */
#define SDRAM_MAMR_8COL /* refresh at 50MHz */ \
#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
| MAMR_G0CLA_A11 /* GPL0 A11[MPC] */ \
| MAMR_RLFA_1X /* Read loop 1 time */ \
| MAMR_WLFA_1X /* Write loop 1 time */ \
| MAMR_TLFA_4X) /* Timer loop 4 times */
/* 8 column SDRAM */
#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
| MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
/* 9 column SDRAM */
#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
| MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
| MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
/* base address 0, 32-bit port, SDRAM UPM, valid */
#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
......
......@@ -68,7 +68,10 @@ typedef struct bd_info {
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62) || defined(CONFIG_SVM_SC8xx)
#if defined(CONFIG_EVB64260) || \
defined(CONFIG_PN62) || \
defined(CONFIG_SXNI855T) || \
defined(CONFIG_SVM_SC8xx)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
......
......@@ -81,6 +81,32 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
/*-----------------------------------------------------------------------
* Definitions for status LED
*/
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#ifdef DEV /* development (debug) settings */
#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
#else /* production settings */
#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
#endif
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
......
......@@ -69,11 +69,25 @@
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/TQM8260/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
......
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