Commit 512bdbb6 authored by Haibo Chen's avatar Haibo Chen

MLK-19223 arm: imx8mm: add MXC_XXX_CLK clock map for imx common code

Now fsl_esdhc driver require the index of  USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.

e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT

This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: 's avatarHaibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
parent c461e51d
......@@ -853,29 +853,42 @@ u32 get_root_clk(enum clk_root_index clock_id)
return root_src_clk / (post_podf + 1) / (pre_podf + 1);
}
unsigned int mxc_get_clock(enum clk_root_index clk)
u32 mxc_get_clock(enum mxc_clock clk)
{
u32 val;
if (clk >= CLK_ROOT_MAX)
return 0;
if (clk == MXC_ARM_CLK) {
return get_root_clk(ARM_A53_CLK_ROOT);
}
if (clk == MXC_IPG_CLK) {
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
switch (clk) {
case MXC_ARM_CLK:
return get_root_clk(ARM_A53_CLK_ROOT);
case MXC_IPG_CLK:
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
case MXC_CSPI_CLK:
return get_root_clk(ECSPI1_CLK_ROOT);
case MXC_ESDHC_CLK:
return get_root_clk(USDHC1_CLK_ROOT);
case MXC_ESDHC2_CLK:
return get_root_clk(USDHC2_CLK_ROOT);
case MXC_ESDHC3_CLK:
return get_root_clk(USDHC3_CLK_ROOT);
case MXC_I2C_CLK:
return get_root_clk(I2C1_CLK_ROOT);
case MXC_UART_CLK:
return get_root_clk(UART1_CLK_ROOT);
case MXC_QSPI_CLK:
return get_root_clk(QSPI_CLK_ROOT);
default:
printf("Unsupported mxc_clock %d\n", clk);
break;
}
return get_root_clk(clk);
return 0;
}
u32 imx_get_uartclk(void)
{
return mxc_get_clock(UART1_CLK_ROOT);
return mxc_get_clock(MXC_UART_CLK);
}
u32 imx_get_fecclk(void)
......@@ -945,11 +958,11 @@ int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
freq = decode_intpll(SYSTEM_PLL3_CLK);
printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(UART1_CLK_ROOT);
freq = mxc_get_clock(MXC_UART_CLK);
printf("UART1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(USDHC1_CLK_ROOT);
freq = mxc_get_clock(MXC_ESDHC_CLK);
printf("USDHC1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(QSPI_CLK_ROOT);
freq = mxc_get_clock(MXC_QSPI_CLK);
printf("QSPI %8d MHz\n", freq / 1000000);
return 0;
......
......@@ -9,6 +9,19 @@
#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
#define _ASM_ARCH_IMX8MM_CLOCK_H
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_IPG_CLK,
MXC_CSPI_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_I2C_CLK,
MXC_UART_CLK,
MXC_QSPI_CLK,
};
enum pll_clocks {
ANATOP_ARM_PLL,
ANATOP_VPU_PLL,
......@@ -33,7 +46,6 @@ enum clk_slice_type {
};
enum clk_root_index {
MXC_ARM_CLK = 0,
ARM_A53_CLK_ROOT = 0,
ARM_M4_CLK_ROOT = 1,
VPU_A53_CLK_ROOT = 2,
......@@ -54,7 +66,6 @@ enum clk_root_index {
AHB_CLK_ROOT = 32,
/* TODO: IPG Not sure */
IPG_CLK_ROOT = 33,
MXC_IPG_CLK = 33,
AUDIO_AHB_CLK_ROOT = 34,
MIPI_DSI_ESC_RX_CLK_ROOT = 36,
DRAM_SEL_CFG = 48,
......@@ -83,12 +94,9 @@ enum clk_root_index {
ENET_PHY_REF_CLK_ROOT = 85,
NAND_CLK_ROOT = 86,
QSPI_CLK_ROOT = 87,
MXC_ESDHC_CLK = 88,
USDHC1_CLK_ROOT = 88,
MXC_ESDHC2_CLK = 89,
USDHC2_CLK_ROOT = 89,
I2C1_CLK_ROOT = 90,
MXC_I2C_CLK = 90,
I2C2_CLK_ROOT = 91,
I2C3_CLK_ROOT = 92,
I2C4_CLK_ROOT = 93,
......@@ -99,7 +107,6 @@ enum clk_root_index {
USB_CORE_REF_CLK_ROOT = 98,
USB_PHY_REF_CLK_ROOT = 99,
GIC_CLK_ROOT = 100,
MXC_CSPI_CLK = 101,
ECSPI1_CLK_ROOT = 101,
ECSPI2_CLK_ROOT = 102,
PWM1_CLK_ROOT = 103,
......@@ -812,7 +819,7 @@ void dram_disable_bypass(void);
u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);
unsigned int mxc_get_clock(enum clk_root_index clk);
u32 mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
......
......@@ -103,7 +103,7 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
......@@ -112,7 +112,7 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
break;
......
......@@ -103,7 +103,7 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
......@@ -112,7 +112,7 @@ int board_mmc_init(bd_t *bis)
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
break;
......
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