Commit 51370d56 authored by York Sun's avatar York Sun Committed by Tom Rini

ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS

These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: default avatarYork Sun <york.sun@nxp.com>
parent 66e399b6
......@@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void)
int i, j, k, m;
u8 *p_8;
u32 *p_32;
struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex) ");
k = 1;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
......@@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void)
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
......@@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void)
puts("\r");
}
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......@@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void)
printf("DDR registers dump for all controllers "
"(zero value is omitted)...\n");
puts("Offset (hex) ");
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
......
......@@ -378,10 +378,10 @@ void fsl_erratum_a007212_workaround(void)
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
#endif
......@@ -409,25 +409,25 @@ void fsl_erratum_a007212_workaround(void)
ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
setbits_be32(plldadcr2, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
setbits_be32(plldadcr3, 0x02000001);
#endif
#endif
setbits_be32(dpdovrcr4, 0xe0000000);
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
#endif
#endif
udelay(100);
clrbits_be32(plldadcr1, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
clrbits_be32(plldadcr2, 0x02000001);
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
clrbits_be32(plldadcr3, 0x02000001);
#endif
#endif
......
......@@ -213,7 +213,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
......@@ -237,7 +237,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
* Simple linear assignment if memory
* controllers are not interleaved.
*/
for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
......
......@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
* Fixed sdram init -- doesn't use serial presence detect.
*/
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
extern fixed_ddr_parm_t fixed_ddr_parm_1[];
#endif
......@@ -56,7 +56,7 @@ phys_size_t fixed_sdram(void)
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
......@@ -76,7 +76,7 @@ phys_size_t fixed_sdram(void)
return 0;
}
} else {
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
/* We require both controllers have identical DIMMs */
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
......
......@@ -23,7 +23,7 @@ config SYS_FSL_DDR_LE
menu "Freescale DDR controllers"
depends on SYS_FSL_DDR
config NUM_DDR_CONTROLLERS
config SYS_NUM_DDR_CTLRS
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A || \
ARCH_T4240
......
......@@ -40,17 +40,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......
......@@ -2318,17 +2318,17 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
case 0:
ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......
......@@ -68,17 +68,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......
......@@ -763,7 +763,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
"regname = %s, value = %s\n",
ctrl_num, regname, value_str);
if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
......@@ -1685,7 +1685,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 1: DIMM SPD data */
if (do_mask & STEP_GET_SPD) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
......@@ -1706,7 +1706,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 2: DIMM Parameters */
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
......@@ -1725,7 +1725,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 3: Common Parameters */
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("\"lowest common\" DIMM parameters: "
......@@ -1739,7 +1739,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 4: User Configuration Options */
if (do_mask & STEP_GATHER_OPTS) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("User Config Options: Controller=%u\n", i);
......@@ -1751,7 +1751,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 5: Address assignment */
if (do_mask & STEP_ASSIGN_ADDRESSES) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
......@@ -1766,7 +1766,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 6: computed controller register values */
if (do_mask & STEP_COMPUTE_REGS) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("Computed Register Values: Controller=%u\n", i);
......
......@@ -40,35 +40,35 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size);
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS,
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
......@@ -146,7 +146,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
unsigned int i;
unsigned int i2c_address = 0;
if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
......@@ -430,7 +430,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
assert_reset = pinfo->board_need_mem_reset();
/* data bus width capacity adjust shift amount */
unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
for (i = first_ctrl; i <= last_ctrl; i++)
dbw_capacity_adjust[i] = 0;
......@@ -720,7 +720,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
&pinfo->common_timing_params[i],
law_memctl, i);
}
#if CONFIG_NUM_DDR_CONTROLLERS > 3
#if CONFIG_SYS_NUM_DDR_CTLRS > 3
else if (i == 2) {
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
fsl_ddr_set_lawbar(
......
......@@ -44,17 +44,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......
......@@ -1077,7 +1077,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
* with 256 Byte is enabled.
*/
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
;
......@@ -1107,39 +1107,39 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
"ctlr_intlv",
"cacheline", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"page", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_PAGE_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"bank", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_BANK_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"superbank", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_1KB", buf)) {
......@@ -1155,7 +1155,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
"3way_8KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_8KB_INTERLEAVING;
#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_1KB", buf)) {
......@@ -1178,7 +1178,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
}
#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
......@@ -1356,10 +1356,10 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
#if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
k = 2;
#else
k = CONFIG_NUM_DDR_CONTROLLERS;
k = CONFIG_SYS_NUM_DDR_CTLRS;
#endif
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
......@@ -1369,7 +1369,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
default:
k = CONFIG_NUM_DDR_CONTROLLERS;
k = CONFIG_SYS_NUM_DDR_CTLRS;
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
......
......@@ -30,17 +30,17 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......@@ -174,23 +174,23 @@ void print_ddr_info(unsigned int start_ctrl)
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
#endif
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
int cas_lat;
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
......@@ -246,7 +246,7 @@ void print_ddr_info(unsigned int start_ctrl)
else
puts(", ECC off)");
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
#ifdef CONFIG_E6500
if (*mcintl3r & 0x80000000) {
puts("\n");
......@@ -268,7 +268,7 @@ void print_ddr_info(unsigned int start_ctrl)
}
#endif
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
......@@ -337,8 +337,8 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
{
unsigned int i;
u32 ddrc_debug20;
u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
struct ccsr_ddr __iomem *ddr;
for (i = first_ctrl; i <= last_ctrl; i++) {
......@@ -346,17 +346,17 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
......
......@@ -62,7 +62,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
......
......@@ -40,7 +40,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
......
......@@ -22,7 +22,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE
......
......@@ -22,7 +22,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE
......
......@@ -53,7 +53,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
......
......@@ -164,7 +164,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
......
......@@ -32,7 +32,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
......
......@@ -26,7 +26,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
......
......@@ -72,7 +72,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
......
......@@ -58,7 +58,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
......
......@@ -48,7 +48,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
......
......@@ -34,7 +34,7 @@
#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
......
......@@ -25,7 +25,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
......
......@@ -15,7 +15,7 @@
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
/* All controllers are for main memory */
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
#endif
#ifdef CONFIG_SYS_FSL_DDR_LE
......@@ -54,7 +54,6 @@ compute_dimm_parameters(const unsigned int ctrl_num,
*
* All data structures have to be on the stack
*/
#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS