Commit 53d76829 authored by York Sun's avatar York Sun

armv7: ls1021a: Move DDR config options to Kconfig

Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.
Signed-off-by: default avatarYork Sun <york.sun@nxp.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
parent 24aaa094
......@@ -3,6 +3,8 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
menu "LS102xA architecture"
depends on ARCH_LS1021A
......@@ -22,6 +24,10 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 1
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
......@@ -34,6 +40,47 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES
bool
config SYS_FSL_DDR
bool "Freescale DDR driver"
help
Select Freescale General DDR driver, shared between most Freescale
PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
based Layerscape SoCs (such as ls2080a).
config SYS_FSL_DDR_BE
bool
default y
help
Access DDR registers in big-endian.
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
config SYS_FSL_DDR_VER_50
bool
config SYS_FSL_DDRC_ARM_GEN3
bool
config SYS_FSL_DDRC_GEN4
bool
config SYS_FSL_DDR3
bool "Freescale DDR3 controller"
depends on !SYS_FSL_DDR4
select SYS_FSL_DDR
select SYS_FSL_DDRC_ARM_GEN3
help
Enable Freescale DDR3 controller on ARM-based SoCs.
config SYS_FSL_DDR4
bool "Freescale DDR4 controller"
select SYS_FSL_DDR
select SYS_FSL_DDRC_GEN4
help
Enable Freescale DDR4 controller.
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
......
......@@ -94,14 +94,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A008407
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
#endif
#define CONFIG_SYS_FSL_DDR
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
#endif
......@@ -121,9 +114,6 @@
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_LS102XA
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
......
......@@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
......@@ -5,7 +5,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_SYS_FSL_DDR4=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
......@@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_SYS_FSL_DDR3=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
......
......@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SYS_FSL_DDR3=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
......@@ -25,6 +25,7 @@ CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
......
......@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_SYS_FSL_DDR3=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
......
......@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_SYS_FSL_DDR3=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
......
......@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SYS_FSL_DDR3=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
......
......@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SYS_FSL_DDR3=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
......
......@@ -127,7 +127,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
......
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