Commit 55aa0bed authored by Thierry Reding's avatar Thierry Reding Committed by Albert ARIBAUD

armv8/mmu: Clean up TCR programming

Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 13a39725
......@@ -103,9 +103,9 @@
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
/* PTWs cacheable, inner/outer WBWA and non-shareable */
/* PTWs cacheable, inner/outer WBWA and inner shareable */
#define TCR_FLAGS (TCR_TG0_64K | \
TCR_SHARED_NON | \
TCR_SHARED_INNER | \
TCR_ORGN_WBWA | \
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
......
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