Commit 5614e71b authored by York Sun's avatar York Sun

Driver/DDR: Moving Freescale DDR driver to a common driver

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent ac688078
......@@ -267,6 +267,7 @@ LIBS-y += drivers/power/ \
drivers/power/battery/
LIBS-y += drivers/spi/
LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
LIBS-y += drivers/serial/
LIBS-y += drivers/usb/eth/
LIBS-y += drivers/usb/gadget/
......
......@@ -423,16 +423,47 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
values is arch specific.
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
SoCs.
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
CONFIG_SYS_FSL_DDRC_GEN1
Freescale DDR1 controller.
CONFIG_SYS_FSL_DDRC_GEN2
Freescale DDR2 controller.
CONFIG_SYS_FSL_DDRC_GEN3
Freescale DDR3 controller.
CONFIG_SYS_FSL_DDR1
Board config to use DDR1. It can be enabled for SoCs with
Freescale DDR1 or DDR2 controllers, depending on the board
implemetation.
CONFIG_SYS_FSL_DDR2
Board config to use DDR2. It can be eanbeld for SoCs with
Freescale DDR2 or DDR3 controllers, depending on the board
implementation.
CONFIG_SYS_FSL_DDR3
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
......@@ -3182,7 +3213,7 @@ FIT uImage format:
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
drivers/ddr/fsl/libddr.o in SPL binary.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
......
......@@ -38,11 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
# Stub implementations of cache management functions for USB
obj-y += cache.o
ifdef CONFIG_FSL_DDR2
obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o
ifdef CONFIG_SYS_FSL_DDR2
obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
else
obj-y += spd_sdram.o
endif
obj-$(CONFIG_FSL_DDR2) += law.o
obj-$(CONFIG_SYS_FSL_DDR2) += law.o
endif # not minimal
......@@ -15,7 +15,7 @@
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
......@@ -99,7 +99,7 @@ void ecc_print_status(void)
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
......
......@@ -29,51 +29,6 @@ obj-$(CONFIG_MP) += release.o
obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
obj-$(CONFIG_CPM2) += commproc.o
# supports ddr1
obj-$(CONFIG_MPC8540) += ddr-gen1.o
obj-$(CONFIG_MPC8560) += ddr-gen1.o
obj-$(CONFIG_MPC8541) += ddr-gen1.o
obj-$(CONFIG_MPC8555) += ddr-gen1.o
# supports ddr1/2
obj-$(CONFIG_MPC8548) += ddr-gen2.o
obj-$(CONFIG_MPC8568) += ddr-gen2.o
obj-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
obj-$(CONFIG_PPC_C29X) += ddr-gen3.o
obj-$(CONFIG_MPC8572) += ddr-gen3.o
obj-$(CONFIG_MPC8536) += ddr-gen3.o
obj-$(CONFIG_MPC8569) += ddr-gen3.o
obj-$(CONFIG_P1010) += ddr-gen3.o
obj-$(CONFIG_P1011) += ddr-gen3.o
obj-$(CONFIG_P1012) += ddr-gen3.o
obj-$(CONFIG_P1013) += ddr-gen3.o
obj-$(CONFIG_P1014) += ddr-gen3.o
obj-$(CONFIG_P1020) += ddr-gen3.o
obj-$(CONFIG_P1021) += ddr-gen3.o
obj-$(CONFIG_P1022) += ddr-gen3.o
obj-$(CONFIG_P1023) += ddr-gen3.o
obj-$(CONFIG_P1024) += ddr-gen3.o
obj-$(CONFIG_P1025) += ddr-gen3.o
obj-$(CONFIG_P2010) += ddr-gen3.o
obj-$(CONFIG_P2020) += ddr-gen3.o
obj-$(CONFIG_PPC_P2041) += ddr-gen3.o
obj-$(CONFIG_PPC_P3041) += ddr-gen3.o
obj-$(CONFIG_PPC_P4080) += ddr-gen3.o
obj-$(CONFIG_PPC_P5020) += ddr-gen3.o
obj-$(CONFIG_PPC_P5040) += ddr-gen3.o
obj-$(CONFIG_PPC_T4240) += ddr-gen3.o
obj-$(CONFIG_PPC_T4160) += ddr-gen3.o
obj-$(CONFIG_PPC_B4420) += ddr-gen3.o
obj-$(CONFIG_PPC_B4860) += ddr-gen3.o
obj-$(CONFIG_BSC9131) += ddr-gen3.o
obj-$(CONFIG_BSC9132) += ddr-gen3.o
obj-$(CONFIG_PPC_T1040) += ddr-gen3.o
obj-$(CONFIG_PPC_T1042) += ddr-gen3.o
obj-$(CONFIG_PPC_T1020) += ddr-gen3.o
obj-$(CONFIG_PPC_T1022) += ddr-gen3.o
obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o
......
......@@ -22,7 +22,7 @@
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
......
......@@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -16,9 +16,6 @@ obj-$(CONFIG_MP) += release.o
obj-y += cpu.o
obj-y += cpu_init.o
# 8610 & 8641 are identical w/regards to DDR
obj-$(CONFIG_MPC8610) += ddr-8641.o
obj-$(CONFIG_MPC8641) += ddr-8641.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-$(CONFIG_MP) += mp.o
......
......@@ -31,9 +31,3 @@ obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/
else
obj-y += ddr/
endif
......@@ -9,10 +9,16 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC83xx
#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
......
......@@ -40,17 +40,20 @@
#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
......@@ -59,6 +62,7 @@
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
......@@ -77,17 +81,20 @@
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8560)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8568)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
......@@ -738,4 +745,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
#endif
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN3)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */
......@@ -7,6 +7,8 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
#define CONFIG_SYS_FSL_DDR_86XX
/* SoC specific defines for Freescale MPC86xx processors */
#if defined(CONFIG_MPC8610)
......
......@@ -279,7 +279,7 @@ typedef struct qesba83xx {
/*
* DDR Memory Controller Memory Map
*/
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
typedef struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
u8 res1[4];
......@@ -739,7 +739,7 @@ typedef struct immap {
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0xE00];
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
#else
ddr83xx_t ddr; /* DDR Memory Controller Memory */
......@@ -1029,7 +1029,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
......
......@@ -3048,11 +3048,11 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
#define CONFIG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
#define CONFIG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
......
......@@ -1253,9 +1253,9 @@ typedef struct immap {
extern immap_t *immr;
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
......
......@@ -9,8 +9,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
......
......@@ -13,7 +13,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
......@@ -89,7 +89,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
......
......@@ -9,11 +9,11 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <fsl_ddr.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
......
......@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
......
......@@ -20,7 +20,7 @@
#include <asm/fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#ifdef CONFIG_PCI
#include <pci.h>
......@@ -134,7 +134,7 @@ void dsp_ddr_configure(void)
*to the DSP DDR controller as connected DDR memories are similar.
*/
ccsr_ddr_t __iomem *pa_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_ddr_t temp_ddr;
ccsr_ddr_t __iomem *dsp_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
......
......@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
......
......@@ -10,14 +10,14 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
......
......@@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include "cpld.h"
......
......@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
......
......@@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
......
......@@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
......
......@@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
......
......@@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
......
......@@ -7,4 +7,4 @@
obj-y += mpc8349emds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
......@@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
......
......@@ -12,8 +12,8 @@
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
#ifdef CONFIG_FSL_DDR2
#include <asm/fsl_ddr_sdram.h>
#ifdef CONFIG_SYS_FSL_DDR2
#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
......@@ -57,7 +57,7 @@ phys_size_t initdram (int board_type)
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_FSL_DDR2
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);
......
......@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
......
......@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
......
......@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
......
......@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
......@@ -168,7 +168,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
......
......@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
......
......@@ -11,7 +11,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
......
......@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,