Commit 588bab19 authored by Ye Li's avatar Ye Li Committed by Jason Liu

MLK-16181 imx8qm/qxp: Add dcache flush to M4 boot commands

For booting M4 running in DDR, we use fatload to load the image to DDR first.
The fatload will do a copy for block size unaligned data in the tail. Since the DDR
area is cachable, so this cause a memory coherence issue. Need to use dcache flush
command before booting the M4 core.

This patch enables the CONFIG_CMD_CACHE and add the dcache flush to M4 boot commands
no matter the M4 runs in DDR or TCM.
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
Reviewed-by: 's avatarPeng Fan <peng.fan@nxp.com>
parent 4b5cfdea
......@@ -5,6 +5,7 @@ CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -5,6 +5,7 @@ CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -5,6 +5,7 @@ CONFIG_TARGET_IMX8QXP_MEK=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -7,6 +7,7 @@ CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -7,6 +7,7 @@ CONFIG_EFI_PARTITION=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -7,6 +7,7 @@ CONFIG_EFI_PARTITION=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
......
......@@ -99,8 +99,8 @@
"m4_1_image=m4_1.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
"m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \
"m4boot_1=run loadm4image_1; bootaux ${loadaddr} 1\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
#ifdef CONFIG_NAND_BOOT
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
......
......@@ -88,7 +88,7 @@
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
#ifdef CONFIG_NAND_BOOT
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
......
......@@ -88,7 +88,7 @@
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
#ifdef CONFIG_NAND_BOOT
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
......
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