Commit 59189a8b authored by Tim Harvey's avatar Tim Harvey Committed by Stefano Babic

ventana: Add Gateworks Ventana family support

Gateworks Ventana is a product family based on the i.MX6.  This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.
Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
parent 1ad6364e
#
# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
# Copyright (C) 2013, Gateworks Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := gw_ventana.o gsc.o
U-Boot for the Gateworks Ventana Product Family boards
This file contains information for the port of U-Boot to the Gateworks
Ventana Product family boards.
1. Boot source, boot from NAND
------------------------------
The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
and bad block information (referred to as 'bootstreams') which are replicated
multiple times in NAND. The number of replications is configurable through
board strapping options and eFUSE settings. The Freescale 'kobs-ng'
application from the Freescale LTIB BSP, which runs under Linux, must be used
to program the bootstream in order to setup the replicated headers correctly.
The Gateworks Ventana boards with NAND flash have been factory programmed
such that their eFUSE settings expect 2 copies of the boostream (this is
specified by providing kobs-ng with the --search_exponent=1 argument). Once in
Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
with:
kobs-ng init -v -x --search_exponent=1 u-boot.imx
The kobs-ng application uses an imximage (u-boot.imx) which contains the
Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware
Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
This information is taken from:
http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
2. Build
--------
There are several Gateworks Ventana boards that share a simliar design but
vary based on CPU, Memory configuration, and subloaded devices. Although
the subloaded devices are handled dynamically in the bootloader using
factory configured EEPROM data to modify the device-tree, the CPU choice
(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
options.
The following Gateworks Ventana configurations exist:
gwventanaq1gspi: MX6Q,1GB,SPI FLASH
gwventanaq : MX6Q,512MB,NAND FLASH
gwventanaq1g : MX6Q,1GB,NAND FLASH
gwventanadl : MX6DL,512MB,NAND FLASH
gwventanadl1g : MX6DL,1GB,NAND FLASH
To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
make gwventanaq1g_config
make
/*
* Copyright (C) 2013 Boundary Devices
* Copyright (C) 2013 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb
/*
* Copyright (C) 2013 Gateworks Corporation
*
* Author: Tim Harvey <tharvey@gateworks.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/errno.h>
#include <common.h>
#include <i2c.h>
#include <linux/ctype.h>
#include "gsc.h"
#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100)
/*
* The Gateworks System Controller will fail to ACK a master transaction if
* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
* When this does occur, it will never be busy long enough to fail more than
* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
* 3 retries.
*/
int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
int retry = 3;
int n = 0;
int ret;
while (n++ < retry) {
ret = i2c_read(chip, addr, alen, buf, len);
if (!ret)
break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret);
if (ret != -ENODEV)
break;
mdelay(10);
}
return ret;
}
int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
int retry = 3;
int n = 0;
int ret;
while (n++ < retry) {
ret = i2c_write(chip, addr, alen, buf, len);
if (!ret)
break;
debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
n, ret);
if (ret != -ENODEV)
break;
mdelay(10);
}
mdelay(1);
return ret;
}
#ifdef CONFIG_CMD_GSC
static void read_hwmon(const char *name, uint reg, uint size, uint low,
uint high)
{
unsigned char buf[3];
uint ui;
printf("%-8s:", name);
memset(buf, 0, sizeof(buf));
if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
puts("fRD\n");
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
if (ui == 0xffffff)
printf("invalid");
else if (ui < low)
printf("%d Failed - Low", ui);
else if (ui > high)
printf("%d Failed - High", ui);
else
printf("%d", ui);
}
puts("\n");
}
int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *model = getenv("model");
i2c_set_bus_num(0);
read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000);
read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000);
read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500);
read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
switch (model[3]) {
case '1': /* GW51xx */
read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
break;
case '2': /* GW52xx */
case '3': /* GW53xx */
read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
break;
case '4': /* GW54xx */
read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
break;
}
return 0;
}
U_BOOT_CMD(gsc, 1, 1, do_gsc,
"GSC test",
""
);
#endif /* CONFIG_CMD_GSC */
/*
* Copyright (C) 2013 Gateworks Corporation
*
* Author: Tim Harvey <tharvey@gateworks.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASSEMBLY__
/* i2c slave addresses */
#define GSC_SC_ADDR 0x20
#define GSC_RTC_ADDR 0x68
#define GSC_HWMON_ADDR 0x29
#define GSC_EEPROM_ADDR 0x51
/* System Controller registers */
enum {
GSC_SC_CTRL0 = 0x00,
GSC_SC_CTRL1 = 0x01,
GSC_SC_STATUS = 0x0a,
GSC_SC_FWVER = 0x0e,
};
/* System Controller Control1 bits */
enum {
GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */
};
/* System Controller Interrupt bits */
enum {
GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
GSC_SC_IRQ_GPIO = 4, /* GPIO change */
GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
};
/* Hardware Monitor registers */
enum {
GSC_HWMON_TEMP = 0x00,
GSC_HWMON_VIN = 0x02,
GSC_HWMON_VDD_3P3 = 0x05,
GSC_HWMON_VBATT = 0x08,
GSC_HWMON_VDD_5P0 = 0x0b,
GSC_HWMON_VDD_CORE = 0x0e,
GSC_HWMON_VDD_HIGH = 0x14,
GSC_HWMON_VDD_DDR = 0x17,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_1P8 = 0x1d,
GSC_HWMON_VDD_2P5 = 0x23,
GSC_HWMON_VDD_1P0 = 0x20,
};
/*
* I2C transactions to the GSC are done via these functions which
* perform retries in the case of a busy GSC NAK'ing the transaction
*/
int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
#endif
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/*
* Copyright (C) 2013 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd, nand, sata
*/
#ifdef CONFIG_SPI_FLASH
BOOT_FROM spi
#else
BOOT_FROM nand
#endif
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* Memory configuration (size is overridden via eeprom config) */
#include "../../boundary/nitrogen6x/ddr-setup.cfg"
#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
#include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
#include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
#else
#error "Unsupported CPU/Memory configuration"
#endif
#include "clocks.cfg"
/*
* Copyright (C) 2013 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _VENTANA_EEPROM_
#define _VENTANA_EEPROM_
struct ventana_board_info {
u8 mac0[6]; /* 0x00: MAC1 */
u8 mac1[6]; /* 0x06: MAC2 */
u8 res0[12]; /* 0x0C: reserved */
u32 serial; /* 0x18: Serial Number (read only) */
u8 res1[4]; /* 0x1C: reserved */
u8 mfgdate[4]; /* 0x20: MFG date (read only) */
u8 res2[7]; /* 0x24 */
/* sdram config */
u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */
u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */
u8 sdram_width; /* 0x2D: enum (32,64) bit */
/* cpu config */
u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */
u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */
u8 model[16]; /* 0x30: model string */
/* FLASH config */
u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */
u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */
/* Config1: SoC Peripherals */
u8 config[8]; /* 0x42: loading options */
u8 res3[4]; /* 0x4A */
u8 chksum[2]; /* 0x4E */
};
/* config bits */
enum {
EECONFIG_ETH0,
EECONFIG_ETH1,
EECONFIG_HDMI_OUT,
EECONFIG_SATA,
EECONFIG_PCIE,
EECONFIG_SSI0,
EECONFIG_SSI1,
EECONFIG_LCD,
EECONFIG_LVDS0,
EECONFIG_LVDS1,
EECONFIG_USB0,
EECONFIG_USB1,
EECONFIG_SD0,
EECONFIG_SD1,
EECONFIG_SD2,
EECONFIG_SD3,
EECONFIG_UART0,
EECONFIG_UART1,
EECONFIG_UART2,
EECONFIG_UART3,
EECONFIG_UART4,
EECONFIG_IPU0,
EECONFIG_IPU1,
EECONFIG_FLEXCAN,
EECONFIG_MIPI_DSI,
EECONFIG_MIPI_CSI,
EECONFIG_TZASC0,
EECONFIG_TZASC1,
EECONFIG_I2C0,
EECONFIG_I2C1,
EECONFIG_I2C2,
EECONFIG_VPU,
EECONFIG_CSI0,
EECONFIG_CSI1,
EECONFIG_CAAM,
EECONFIG_MEZZ,
EECONFIG_RES1,
EECONFIG_RES2,
EECONFIG_RES3,
EECONFIG_RES4,
EECONFIG_ESPCI0,
EECONFIG_ESPCI1,
EECONFIG_ESPCI2,
EECONFIG_ESPCI3,
EECONFIG_ESPCI4,
EECONFIG_ESPCI5,
EECONFIG_RES5,
EECONFIG_RES6,
EECONFIG_GPS,
EECONFIG_SPIFL0,
EECONFIG_SPIFL1,
EECONFIG_GSPBATT,
EECONFIG_HDMI_IN,
EECONFIG_VID_OUT,
EECONFIG_VID_IN,
EECONFIG_NAND,
EECONFIG_RES8,
EECONFIG_RES9,
EECONFIG_RES10,
EECONFIG_RES11,
EECONFIG_RES12,
EECONFIG_RES13,
EECONFIG_RES14,
EECONFIG_RES15,
};
#endif
......@@ -320,6 +320,11 @@ Active arm armv7 mx6 freescale mx6qsabreauto
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
......
This diff is collapsed.
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