Commit 595af9db authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

parents 03bfc783 35c4ce5e
......@@ -21,6 +21,7 @@
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
#include <mmc.h>
enum ldo_reg {
LDO_ARM,
......@@ -355,7 +356,7 @@ __weak int board_mmc_get_env_dev(int devno)
return CONFIG_SYS_MMC_ENV_DEV;
}
int mmc_get_env_dev(void)
static int mmc_get_boot_dev(void)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 soc_sbmr = readl(&src_regs->sbmr1);
......@@ -370,15 +371,44 @@ int mmc_get_env_dev(void)
*/
bootsel = (soc_sbmr & 0x000000FF) >> 6;
/* If not boot from sd/mmc, use default value */
/* No boot from sd/mmc */
if (bootsel != 1)
return CONFIG_SYS_MMC_ENV_DEV;
return -1;
/* BOOT_CFG2[3] and BOOT_CFG2[4] */
devno = (soc_sbmr & 0x00001800) >> 11;
return devno;
}
int mmc_get_env_dev(void)
{
int devno = mmc_get_boot_dev();
/* If not boot from sd/mmc, use default value */
if (devno < 0)
return CONFIG_SYS_MMC_ENV_DEV;
return board_mmc_get_env_dev(devno);
}
#ifdef CONFIG_SYS_MMC_ENV_PART
__weak int board_mmc_get_env_part(int devno)
{
return CONFIG_SYS_MMC_ENV_PART;
}
uint mmc_get_env_part(struct mmc *mmc)
{
int devno = mmc_get_boot_dev();
/* If not boot from sd/mmc, use default value */
if (devno < 0)
return CONFIG_SYS_MMC_ENV_PART;
return board_mmc_get_env_part(devno);
}
#endif
#endif
int board_postclk_init(void)
......@@ -537,3 +567,41 @@ void imx_setup_hdmi(void)
writel(reg, &mxc_ccm->chsccdr);
}
#endif
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
struct src *src_reg;
u32 stack, pc;
if (!boot_private_data)
return -EINVAL;
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
src_reg = (struct src *)SRC_BASE_ADDR;
clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
SRC_SCR_M4_ENABLE_MASK);
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
unsigned val;
val = readl(&src_reg->scr);
if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
return 0; /* assert in reset */
return 1;
}
#endif
......@@ -1067,6 +1067,12 @@ void clock_init(void)
#ifdef CONFIG_NAND_MXS
clock_enable(CCGR_RAWNAND, 1);
#endif
if (IS_ENABLED(CONFIG_IMX_RDC)) {
clock_enable(CCGR_RDC, 1);
clock_enable(CCGR_SEMA1, 1);
clock_enable(CCGR_SEMA2, 1);
}
}
#ifdef CONFIG_SECURE_BOOT
......
......@@ -12,6 +12,8 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <asm/imx-common/hab.h>
#include <asm/imx-common/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
......@@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = {
};
#endif
#ifdef CONFIG_IMX_RDC
/*
* In current design, if any peripheral was assigned to both A7 and M4,
* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
* low power mode. So M4 sleep will cause some peripherals fail to work
* at A7 core side. At default, all resources are in domain 0 - 3.
*
* There are 26 peripherals impacted by this IC issue:
* SIM2(sim2/emvsim2)
* SIM1(sim1/emvsim1)
* UART1/UART2/UART3/UART4/UART5/UART6/UART7
* SAI1/SAI2/SAI3
* WDOG1/WDOG2/WDOG3/WDOG4
* GPT1/GPT2/GPT3/GPT4
* PWM1/PWM2/PWM3/PWM4
* ENET1/ENET2
* Software Workaround:
* Here we setup some resources to domain 0 where M4 codes will move
* the M4 out of this domain. Then M4 is not able to access them any longer.
* This is a workaround for ic issue. So the peripherals are not shared
* by them. This way requires the uboot implemented the RDC driver and
* set the 26 IPs above to domain 0 only. M4 code will assign resource
* to its own domain, if it want to use the resource.
*/
static rdc_peri_cfg_t const resources[] = {
(RDC_PER_SIM1 | RDC_DOMAIN(0)),
(RDC_PER_SIM2 | RDC_DOMAIN(0)),
(RDC_PER_UART1 | RDC_DOMAIN(0)),
(RDC_PER_UART2 | RDC_DOMAIN(0)),
(RDC_PER_UART3 | RDC_DOMAIN(0)),
(RDC_PER_UART4 | RDC_DOMAIN(0)),
(RDC_PER_UART5 | RDC_DOMAIN(0)),
(RDC_PER_UART6 | RDC_DOMAIN(0)),
(RDC_PER_UART7 | RDC_DOMAIN(0)),
(RDC_PER_SAI1 | RDC_DOMAIN(0)),
(RDC_PER_SAI2 | RDC_DOMAIN(0)),
(RDC_PER_SAI3 | RDC_DOMAIN(0)),
(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
(RDC_PER_GPT1 | RDC_DOMAIN(0)),
(RDC_PER_GPT2 | RDC_DOMAIN(0)),
(RDC_PER_GPT3 | RDC_DOMAIN(0)),
(RDC_PER_GPT4 | RDC_DOMAIN(0)),
(RDC_PER_PWM1 | RDC_DOMAIN(0)),
(RDC_PER_PWM2 | RDC_DOMAIN(0)),
(RDC_PER_PWM3 | RDC_DOMAIN(0)),
(RDC_PER_PWM4 | RDC_DOMAIN(0)),
(RDC_PER_ENET1 | RDC_DOMAIN(0)),
(RDC_PER_ENET2 | RDC_DOMAIN(0)),
};
static void isolate_resource(void)
{
imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
}
#endif
#if defined(CONFIG_SECURE_BOOT)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
.bank = 1,
......@@ -163,6 +224,9 @@ int arch_cpu_init(void)
mxs_dma_init();
#endif
if (IS_ENABLED(CONFIG_IMX_RDC))
isolate_resource();
return 0;
}
......@@ -211,6 +275,42 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
u32 stack, pc;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
if (!boot_private_data)
return 1;
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
SRC_M4RCR_ENABLE_M4_MASK);
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
{
uint32_t val;
struct src *src_reg = (struct src *)SRC_BASE_ADDR;
val = readl(&src_reg->m4rcr);
if (val & 0x00000001)
return 0; /* assert in reset */
return 1;
}
#endif
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);
......
......@@ -3,3 +3,17 @@ config IMX_CONFIG
config ROM_UNIFIED_SECTIONS
bool
config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7
help
i.MX Resource domain controller is used to assign masters
and peripherals to differet domains. This can be used to
isolate resources.
config IMX_BOOTAUX
bool "Support boot auxiliary core"
depends on ARCH_MX7 || ARCH_MX6
help
bootaux [addr] to boot auxiliary core.
......@@ -27,6 +27,8 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
......
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
/* Allow for arch specific config before we boot */
static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
}
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
__attribute__((weak, alias("__arch_auxiliary_core_up")));
/* Allow for arch specific config before we boot */
static int __arch_auxiliary_core_check_up(u32 core_id)
{
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
}
int arch_auxiliary_core_check_up(u32 core_id)
__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
/*
* To i.MX6SX and i.MX7D, the image supported by bootaux needs
* the reset vector at the head for the image, with SP and PC
* as the first two words.
*
* Per the cortex-M reference manual, the reset vector of M4 needs
* to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
* of that vector. So to boot M4, the A core must build the M4's reset
* vector with getting the PC and SP from image and filling them to
* TCMUL. When M4 is kicked, it will load the PC and SP by itself.
* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4 TCMUL.
*/
int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
int ret, up;
if (argc < 2)
return CMD_RET_USAGE;
up = arch_auxiliary_core_check_up(0);
if (up) {
printf("## Auxiliary core is already up\n");
return CMD_RET_SUCCESS;
}
addr = simple_strtoul(argv[1], NULL, 16);
printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
ret = arch_auxiliary_core_up(0, addr);
if (ret)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
"Start auxiliary core",
""
);
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm-generic/errno.h>
/*
* Check if the RDC Semaphore is required for this peripheral.
*/
static inline int imx_rdc_check_sema_required(int per_id)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg;
reg = readl(&imx_rdc->pdap[per_id]);
/*
* No semaphore:
* Intial value or this peripheral is assigned to only one domain
*/
if (!(reg & RDC_PDAP_SREQ_MASK))
return -ENOENT;
return 0;
}
/*
* Check the peripheral read / write access permission on Domain [dom_id].
*/
int imx_rdc_check_permission(int per_id, int dom_id)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg;
reg = readl(&imx_rdc->pdap[per_id]);
if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
return -EACCES; /*No access*/
return 0;
}
/*
* Lock up the RDC semaphore for this peripheral if semaphore is required.
*/
int imx_rdc_sema_lock(int per_id)
{
struct rdc_sema_regs *imx_rdc_sema;
int ret;
u8 reg;
ret = imx_rdc_check_sema_required(per_id);
if (ret)
return ret;
if (per_id < SEMA_GATES_NUM)
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
else
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
do {
writeb(RDC_SEMA_PROC_ID,
&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
break; /* Get the Semaphore*/
} while (1);
return 0;
}
/*
* Unlock the RDC semaphore for this peripheral if main CPU is the
* semaphore owner.
*/
int imx_rdc_sema_unlock(int per_id)
{
struct rdc_sema_regs *imx_rdc_sema;
int ret;
u8 reg;
ret = imx_rdc_check_sema_required(per_id);
if (ret)
return ret;
if (per_id < SEMA_GATES_NUM)
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
else
imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
return 1; /*Not the semaphore owner */
writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
return 0;
}
/*
* Setup RDC setting for one peripheral
*/
int imx_rdc_setup_peri(rdc_peri_cfg_t p)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 reg = 0;
u32 share_count = 0;
u32 peri_id = p & RDC_PERI_MASK;
u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
/* No domain assigned */
if (domain == 0)
return -EINVAL;
reg |= domain;
share_count = (domain & 0x3)
+ ((domain >> 2) & 0x3)
+ ((domain >> 4) & 0x3)
+ ((domain >> 6) & 0x3);
if (share_count > 0x3)
reg |= RDC_PDAP_SREQ_MASK;
writel(reg, &imx_rdc->pdap[peri_id]);
return 0;
}
/*
* Setup RDC settings for multiple peripherals
*/
int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
unsigned count)
{
rdc_peri_cfg_t const *p = peripherals_list;
int i, ret;
for (i = 0; i < count; i++) {
ret = imx_rdc_setup_peri(*p);
if (ret)
return ret;
p++;
}
return 0;
}
/*
* Setup RDC setting for one master
*/
int imx_rdc_setup_ma(rdc_ma_cfg_t p)
{
struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
return 0;
}
/*
* Setup RDC settings for multiple masters
*/
int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
{
rdc_ma_cfg_t const *p = masters_list;
int i, ret;
for (i = 0; i < count; i++) {
ret = imx_rdc_setup_ma(*p);
if (ret)
return ret;
p++;
}
return 0;
}
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_RDC_H__
#define __IMX_RDC_H__
#if defined(CONFIG_MX6SX)
#include "mx6sx_rdc.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SX */
#endif /* __IMX_RDC_H__*/
......@@ -356,6 +356,30 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
struct rdc_regs {
u32 vir; /* Version information */
u32 reserved1[8];
u32 stat; /* Status */
u32 intctrl; /* Interrupt and Control */
u32 intstat; /* Interrupt Status */
u32 reserved2[116];
u32 mda[32]; /* Master Domain Assignment */
u32 reserved3[96];
u32 pdap[104]; /* Peripheral Domain Access Permissions */
u32 reserved4[88];
struct {
u32 mrsa; /* Memory Region Start Address */
u32 mrea; /* Memory Region End Address */
u32 mrc; /* Memory Region Control */
u32 mrvs; /* Memory Region Violation Status */
} mem_region[55];
};
struct rdc_sema_regs {
u8 gate[64]; /* Gate */
u16 rstgt; /* Reset Gate */
};
/* WEIM registers */
struct weim {
u32 cs0gcr1;
......@@ -414,6 +438,11 @@ struct src {
u32 gpr10;
};
#define SRC_SCR_M4_ENABLE_OFFSET 22
#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
/* GPR1 bitfields */
#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
......
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX6SX_RDC_H__
#define __MX6SX_RDC_H__
#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
enum {
RDC_PER_PWM1 = 0,
RDC_PER_PWM2,
RDC_PER_PWM3,
RDC_PER_PWM4,
RDC_PER_CAN1,
RDC_PER_CAN2,
RDC_PER_GPT,
RDC_PER_GPIO1,
RDC_PER_GPIO2,
RDC_PER_GPIO3,
RDC_PER_GPIO4,
RDC_PER_GPIO5,
RDC_PER_GPIO6,
RDC_PER_GPIO7,
RDC_PER_KPP,
RDC_PER_WDOG1,
RDC_PER_WODG2,
RDC_PER_CCM,
RDC_PER_ANATOPDIG,
RDC_PER_SNVSHP,
RDC_PER_EPIT1,
RDC_PER_EPIT2,
RDC_PER_SRC,
RDC_PER_GPC,
RDC_PER_IOMUXC,
RDC_PER_IOMUXCGPR,
RDC_PER_CANFD1,
RDC_PER_SDMA,
RDC_PER_CANFD2,
RDC_PER_SEMA1,
RDC_PER_SEMA2,
RDC_PER_RDC,
RDC_PER_AIPSTZ1_GE1,
RDC_PER_AIPSTZ2_GE2,
RDC_PER_USBO2H_PL301,
RDC_PER_USBO2H_USB,
RDC_PER_ENET1,
RDC_PER_MLB25,
RDC_PER_USDHC1,
RDC_PER_USDHC2,
RDC_PER_USDHC3,
RDC_PER_USDHC4,
RDC_PER_I2C1,
RDC_PER_I2C2,
RDC_PER_I2C3,
RDC_PER_ROMCP,
RDC_PER_MMDC,
RDC_PER_ENET2,
RDC_PER_EIM,
RDC_PER_OCOTP,
RDC_PER_CSU,
RDC_PER_PERFMON1,
RDC_PER_PERFMON2,
RDC_PER_AXIMON,
RDC_PER_TZASC1,
RDC_PER_SAI1,
RDC_PER_AUDMUX,
RDC_PER_SAI2,
RDC_PER_QSPI1,
RDC_PER_QSPI2,
RDC_PER_UART2,
RDC_PER_UART3,
RDC_PER_UART4,
RDC_PER_UART5,
RDC_PER_I2C4,
RDC_PER_QOSC,
RDC_PER_CAAM,
RDC_PER_DAP,
RDC_PER_ADC1,
RDC_PER_ADC2,
RDC_PER_WDOG3,
RDC_PER_ECSPI5,
RDC_PER_SEMA4,
RDC_PER_MUPORT1,
RDC_PER_CANFD_CPU,
RDC_PER_MUPORT2,
RDC_PER_UART6,
RDC_PER_PWM5,
RDC_PER_PWM6,
RDC_PER_PWM7,
RDC_PER_PWM8,
RDC_PER_AIPSTZ3_GE0,
RDC_PER_AIPSTZ3_GE1,
RDC_PER_RESERVED1,
RDC_PER_SPDIF,
RDC_PER_ECSPI1,
RDC_PER_ECSPI2,
RDC_PER_ECSPI3,
RDC_PER_ECSPI4,
RDC_PER_RESERVED2,
RDC_PER_RESERVED3,
RDC_PER_UART1,
RDC_PER_ESAI,
RDC_PER_SSI1,
RDC_PER_SSI2,
RDC_PER_SSI3,
RDC_PER_ASRC,
RDC_PER_RESERVED4,
RDC_PER_SPBA_MA,
RDC_PER_GIS,
RDC_PER_DCIC1,
RDC_PER_DCIC2,
RDC_PER_CSI1,
RDC_PER_PXP,
RDC_PER_CSI2,
RDC_PER_LCDIF1,
RDC_PER_LCDIF2,
RDC_PER_VADC,
RDC_PER_VDEC,
RDC_PER_SPBA_DISPLAYMIX,
};
enum {
RDC_MA_A9_L2CACHE = 0,
RDC_MA_M4,
RDC_MA_GPU,
RDC_MA_CSI1,
RDC_MA_CSI2,
RDC_MA_LCDIF1,
RDC_MA_LCDIF2,
RDC_MA_PXP,
RDC_MA_PCIE_CTRL,
RDC_MA_DAP,
RDC_MA_CAAM,
RDC_MA_SDMA_PERI,
RDC_MA_SDMA_BURST,
RDC_MA_APBHDMA,
RDC_MA_RAWNAND,
RDC_MA_USDHC1,
RDC_MA_USDHC2,
RDC_MA_USDHC3,
RDC_MA_USDHC4,
RDC_MA_USB,
RDC_MA_MLB,