Commit 5a1095a8 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

parents 6af857c5 d145878d
......@@ -1378,6 +1378,10 @@ The following options need to be configured:
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
- PWM Support:
CONFIG_PWM_IMX
Support for PWM modul on the imx6.
- TPM Support:
CONFIG_TPM
Support TPM devices.
......@@ -2949,6 +2953,17 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
currently Xilinx Zynq qspi support these type of connections.
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128.
The status register write enable/disable bit, combined with
the W#/VPP signal provides hardware data protection for the
device as follows: When the enable/disable bit is set to 1,
and the W#/VPP signal is driven LOW, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute. The only way to exit this
hardware-protected mode is to drive W#/VPP HIGH.
- SystemACE Support:
CONFIG_SYSTEMACE
......
......@@ -509,6 +509,9 @@ config TARGET_CGTQMX6EVAL
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
config TARGET_ARISTAINETOS
bool "Support aristainetos"
config TARGET_MX6QARM2
bool "Support mx6qarm2"
......@@ -521,6 +524,9 @@ config TARGET_MX6SABRESD
config TARGET_MX6SLEVK
bool "Support mx6slevk"
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
config TARGET_GW_VENTANA
bool "Support gw_ventana"
......@@ -770,6 +776,7 @@ config TARGET_JORNADA
endchoice
source "board/8dtech/eco5pk/Kconfig"
source "board/aristainetos/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
......@@ -877,6 +884,7 @@ source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
......
......@@ -10,3 +10,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_MP) += mp.o
......@@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
}
#endif
/* spi_num can be from 0 - SPI_MAX_NUM */
int enable_spi_clk(unsigned char enable, unsigned spi_num)
{
u32 reg;
u32 mask;
if (spi_num > SPI_MAX_NUM)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
reg = __raw_readl(&imx_ccm->CCGR1);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR1);
return 0;
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;
......@@ -214,7 +232,7 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
#endif
......@@ -282,7 +300,7 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
......@@ -355,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);
#ifdef CONFIG_MX6SX
/*
* Set enet ahb clock to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
*/
reg = readl(&imx_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
| MXC_CCM_CHSCCDR_ENET_PODF_MASK
| MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
/* PLL2 PFD2 */
reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
/* Div = 2*/
reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
writel(reg, &imx_ccm->chsccdr);
/* Enable enet system clock */
reg = readl(&imx_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_ENET_MASK;
writel(reg, &imx_ccm->CCGR3);
#endif
return 0;
}
#endif
......@@ -437,6 +476,7 @@ static int enable_enet_pll(uint32_t en)
return 0;
}
#ifndef CONFIG_MX6SX
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
......@@ -445,6 +485,7 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
static void ungate_pcie_clock(void)
{
......@@ -455,11 +496,13 @@ static void ungate_pcie_clock(void)
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
#endif
int enable_pcie_clock(void)
{
......@@ -491,7 +534,9 @@ int enable_pcie_clock(void)
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
#ifndef CONFIG_MX6SX
ungate_sata_clock();
#endif
ungate_pcie_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
......@@ -573,6 +618,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#ifndef CONFIG_MX6SX
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
......@@ -581,6 +627,7 @@ void enable_ipu_clock(void)
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
#endif
/***************************************************/
U_BOOT_CMD(
......
......@@ -197,6 +197,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
u16 CS0_END;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr;
int clkper; /* clock period in picoseconds */
int clock; /* clock freq in mHz */
int cs;
......@@ -422,8 +423,13 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
mmdc0->mdor = reg;
/* Step 5: Configure DDR physical parameters (density and burst len) */
coladdr = m->coladdr;
if (m->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr += 4;
else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
coladdr += 1;
reg = (m->rowaddr - 11) << 24 | /* ROW */
(m->coladdr - 9) << 20 | /* COL */
(coladdr - 9) << 20 | /* COL */
(1 << 19) | /* Burst Length = 8 for DDR3 */
(i->dsize << 16); /* DDR data bus size */
mmdc0->mdctl = reg;
......
/*
* (C) Copyright 2014
* Gabriel Huau <contact@huau-gabriel.fr>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#define MAX_CPUS 4
static struct src *src = (struct src *)SRC_BASE_ADDR;
static uint32_t cpu_reset_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_RESET_MASK,
SRC_SCR_CORE_2_RESET_MASK,
SRC_SCR_CORE_3_RESET_MASK
};
static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_ENABLE_MASK,
SRC_SCR_CORE_2_ENABLE_MASK,
SRC_SCR_CORE_3_ENABLE_MASK
};
int cpu_reset(int nr)
{
/* Software reset of the CPU N */
src->scr |= cpu_reset_mask[nr];
return 0;
}
int cpu_status(int nr)
{
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
return 0;
}
int cpu_release(int nr, int argc, char *const argv[])
{
uint32_t boot_addr;
boot_addr = simple_strtoul(argv[0], NULL, 16);
switch (nr) {
case 1:
src->gpr3 = boot_addr;
break;
case 2:
src->gpr5 = boot_addr;
break;
case 3:
src->gpr7 = boot_addr;
break;
default:
return 1;
}
/* CPU N is ready to start */
src->scr |= cpu_ctrl_mask[nr];
return 0;
}
int is_core_valid(unsigned int core)
{
uint32_t nr_cores = get_nr_cpus();
if (core > nr_cores)
return 0;
return 1;
}
int cpu_disable(int nr)
{
/* Disable the CPU N */
src->scr &= ~cpu_ctrl_mask[nr];
return 0;
}
......@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
return readl(&scu->config) & 3;
}
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
......@@ -79,9 +85,15 @@ u32 __weak get_board_rev(void)
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
struct aipstz_regs *aips3;
#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
......@@ -107,6 +119,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
#ifdef CONFIG_MX6SX
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
#endif
}
static void clear_ldo_ramp(void)
......@@ -311,6 +343,10 @@ void s_init(void)
u32 mask480;
u32 mask528;
if (is_cpu_type(MXC_CPU_MX6SX))
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
......
......@@ -93,6 +93,11 @@ unsigned imx_ddr_size(void)
bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
bits += ESD_MMDC_CTL_GET_CS1(ctl);
/* The MX6 can do only 3840 MiB of DRAM */
if (bits == 32)
return 0xf0000000;
return 1 << bits;
}
#endif
......@@ -112,6 +117,8 @@ const char *get_imx_type(u32 imxtype)
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
......
......@@ -12,8 +12,7 @@
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
......
......@@ -8,6 +8,7 @@
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SOLO 0x62
#define MXC_CPU_MX6SX 0x62
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
......@@ -40,7 +40,7 @@ struct mxc_ccm_reg {
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
u32 chscdr;
u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
......
......@@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
#endif /* __ASM_ARCH_CLOCK_H */
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......@@ -65,6 +65,16 @@
#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
......
......@@ -13,7 +13,11 @@
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl-ddr.h"
#else
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
......
......@@ -35,6 +35,8 @@ enum {
};
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
#include "mx6sx_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6Q */
......
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6SX_DDR_H__
#define __ASM_ARCH_MX6SX_DDR_H__
#ifndef CONFIG_MX6SX
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e02ec
#define MX6_IOM_DRAM_DQM1 0x020e02f0
#define MX6_IOM_DRAM_DQM2 0x020e02f4
#define MX6_IOM_DRAM_DQM3 0x020e02f8
#define MX6_IOM_DRAM_RAS 0x020e02fc
#define MX6_IOM_DRAM_CAS 0x020e0300
#define MX6_IOM_DRAM_SDODT0 0x020e0310
#define MX6_IOM_DRAM_SDODT1 0x020e0314
#define MX6_IOM_DRAM_SDBA2 0x020e0320
#define MX6_IOM_DRAM_SDCKE0 0x020e0324
#define MX6_IOM_DRAM_SDCKE1 0x020e0328
#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
#define MX6_IOM_DRAM_RESET 0x020e0340
#define MX6_IOM_DRAM_SDQS0 0x020e0330
#define MX6_IOM_DRAM_SDQS1 0x020e0334
#define MX6_IOM_DRAM_SDQS2 0x020e0338
#define MX6_IOM_DRAM_SDQS3 0x020e033c
#define MX6_IOM_GRP_ADDDS 0x020e05f4
#define MX6_IOM_DDRMODE_CTL 0x020e05f8
#define MX6_IOM_GRP_DDRPKE 0x020e05fc
#define MX6_IOM_GRP_DDRMODE 0x020e0608
#define MX6_IOM_GRP_B0DS 0x020e060c
#define MX6_IOM_GRP_B1DS 0x020e0610
#define MX6_IOM_GRP_CTLDS 0x020e0614
#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
#define MX6_IOM_GRP_B2DS 0x020e061c
#define MX6_IOM_GRP_B3DS 0x020e0620
#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -14,6 +14,7 @@
#define soc_rev() (get_cpu_rev() & 0xFF)
#define is_soc_rev(rev) (soc_rev() - rev)
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
......
if TARGET_ARISTAINETOS
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "aristainetos"
config SYS_SOC
string
default "mx6"
config SYS_CONFIG_NAME
string
default "aristainetos"
endif
ARISTAINETOS BOARD
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/aristainetos/
F: include/configs/aristainetos.h
F: configs/aristainetos_defconfig
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := aristainetos.o
This diff is collapsed.
/*
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "mt41j128M.cfg"
#include "clocks.cfg"
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00c03f3f
DATA 4, CCM_CCGR1, 0x0030fcff
DATA 4, CCM_CCGR2, 0x0fffcfc0
DATA 4, CCM_CCGR3, 0x3ff0300f
DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0f0000c3
DATA 4, CCM_CCGR6, 0x000003ff
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR IO TYPE */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
/* Clock */
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
/* Address */
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* Control */
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
/* Data Strobe */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ZQ Calibration */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/*
* DQS gating, read delay, write delay calibration values
* based on calibration compare of 0x00ffff00
*/
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurment */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* in DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db