Commit 5da627a4 authored by wdenk's avatar wdenk

* Patch by Steven Scholz, 10 Oct 2003

  - Add support for Altera FPGA ACEX1K

* Patches by Thomas Lange, 09 Oct 2003:
  - Endian swap ATA identity for all big endian CPUs, not just PPC
  - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
    args to linux
  - add support for dbau1x00 board (MIPS32)
parent 15647dc7
......@@ -2,11 +2,18 @@
Changes for U-Boot 1.0.0:
======================================================================
* Patch by Steven Scholz, 10 Oct 2003
- Add support for Altera FPGA ACEX1K
* Patches by Thomas Lange, 09 Oct 2003:
- fix cmd_ide.c for non ppc boards (read/write functions did not
add ATA base address)
- fix for shannon board
- #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
- Endian swap ATA identity for all big endian CPUs, not just PPC
- MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
args to linux
- add support for dbau1x00 board (MIPS32)
* Patch by Sangmoon Kim, 07 Oct 2003:
add support for debris board
......
......@@ -75,7 +75,7 @@ E: clark@esteem.com
D: ESTEEM192E support
N: Magnus Damm
E: eramdam@kieray1.p.y.ki.era.ericsson.se
E: damm@opensource.se
D: 8xxrom
N: Arun Dharankar
......@@ -191,8 +191,8 @@ E: tkoeller@gmx.net
D: Port to Motorola Sandpoint 3 (MPC8240)
N: Thomas Lange
E: thomas@corelatus.com
D: Support for GTH board; lots of PCMCIA fixes
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
N: The LEOX team
E: team@leox.org
......
......@@ -162,7 +162,7 @@ Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
Thomas Lange <thomas@corelatus.com>
Thomas Lange <thomas@corelatus.se>
GTH MPC860
......@@ -341,6 +341,9 @@ Wolfgang Denk <wd@denx.de>
incaip MIPS32 4Kc
purple MIPS64 5Kc
Thomas Lange <thomas@corelatus.se>
dbau1x00 MIPS32 Au1000
#########################################################################
# Nios-32 Systems: #
# #
......
......@@ -137,14 +137,16 @@ LIST_pxa="cradle csb226 innokom lubbock wepep250"
LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
#########################################################################
## MIPS 4Kc Systems
## MIPS Systems
#########################################################################
LIST_mips4kc="incaip"
LIST_mips5kc="purple"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
LIST_au1x00="dbau1x00"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
#########################################################################
## i386 Systems
......
......@@ -958,6 +958,12 @@ DK1C20_config: unconfig
@./mkconfig $(@:_config=) nios nios dk1c20
#########################################################################
## MIPS32 AU1000
#########################################################################
dbau1x00_config : unconfig
@./mkconfig $(@:_config=) mips mips dbau1x00
#########################################################################
#########################################################################
......
......@@ -398,15 +398,16 @@ The following options need to be configured:
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
- 8xx CPU Options: (if using an 8xx cpu)
Define one or more of
CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() can not work e.g.
no 32KHz reference PIT/RTC clock
CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() cannot work
e.g. if there is no 32KHz
reference PIT/RTC clock
- Clock Interface:
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
U-Boot stores all clock information in Hz
......@@ -416,11 +417,16 @@ The following options need to be configured:
"clocks_in_mhz" can be defined so that U-Boot
converts clock data to MHZ before passing it to the
Linux kernel.
When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
"clocks_in_mhz=1" is automatically included in the
default environment.
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transfering memsize parameter to linux, some versions
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
- Console Interface:
Depending on board, define exactly one serial port
(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
......
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
SOBJS = memsetup.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
By Thomas.Lange@corelatus.se 2003-10-06
----------------------------------------
DbAu1000 is a development board from AMD containing
an Alchemy AU1000 with mips32 core.
Limitations & comments
----------------------
I assume that you set board to BIG endian!
Little endian not tested, most probably broken.
I named the board dbau1x00, to allow
support for all three development boards
some day ( dbau1000, dbau1100 and dbau1500 ).
I only have a dbau1000, so all testing is limited
to this board!
The board has two different flash banks, that can
be selected via dip switch. This makes it possible
to test new bootloaders without thrashing the YAMON
boot loader deliviered with board.
Ethernet only supported for mac0.
Pcmcia only supported for slot 0, only 3.3V.
Pcmcia IDE tested with Sandisk Compact Flash and
IBM microdrive.
###################################
######## NOTE!!!!!! #########
###################################
If you partition a disk on another system (e.g. laptop),
all bytes will be swapped on 16bit level when using
PCMCIA!!!!
This is probably due to an error in Au1000 chip.
Solution:
a) Boot via network and partition disk directly from
dbau1x00. The endian will then be correct.
b) Partition disk on "laptop" and fill it with all files
you need. Then write a simple program that endian swaps
whole disk,
Example:
Original "laptop" byte order:
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
Dbau1000 byte order will then be:
B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
#
# ROM version
TEXT_BASE = 0xbfc00000
# RAM version
#TEXT_BASE = 0x80100000
/*
* (C) Copyright 2003
* Thomas.Lange@corelatus.se
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
long int initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return 64*1024*1024;
}
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
/* In cpu/mips/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
int checkboard (void)
{
u16 status;
volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
u32 proc_id;
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
switch(proc_id>>24){
case 0:
puts("Board: Merlot (DbAu1000)\n");
printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
(proc_id>>8)&0xFF,proc_id&0xFF);
break;
default:
printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id);
}
#ifdef CONFIG_IDE_PCMCIA
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */
status = 4;
*pcmcia_bcsr = status;
status |= BCSR_PCMCIA_PC0DRVEN;
*pcmcia_bcsr = status;
au_sync();
udelay(300*1000);
status |= BCSR_PCMCIA_PC0RST;
*pcmcia_bcsr = status;
au_sync();
udelay(100*1000);
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
#if 0
/* We dont need theese unless we run whole pcmcia package */
write_one_tlb(20, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_IO_BASE, /* Hi */
0x3C000017, /* Lo0 */
0x3C200017); /* Lo1 */
write_one_tlb(21, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_ATTR_BASE, /* Hi */
0x3D000017, /* Lo0 */
0x3D200017); /* Lo1 */
#endif
write_one_tlb(22, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_MEM_ADDR, /* Hi */
0x3E000017, /* Lo0 */
0x3E200017); /* Lo1 */
/* Release reset of ethernet PHY chips */
/* Always do this, because linux does not know about it */
*phy = 3;
return 0;
#endif
}
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
printf ("Skipping flash_init\n");
return (0);
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
printf ("write_buff not implemented\n");
return (-1);
}
/* Memory sub-system initialization code */
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
.globl memsetup
memsetup:
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
nop
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDADDR0
li t1, 0x001003F8
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x001023F8
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x64000C24 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x66000C24 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000033
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD1
li t1, 0x00000033
sw t1, 0(t0)
sync
/* Static memory controller */
/* RCE0 AMD 29LV640M MirrorBit Flash */
li t0, MEM_STCFG0
li t1, 0x00000003
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x22080b20
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
/* RCE1 CPLD Board Logic */
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
/* RCE3 PCMCIA 250ns */
li t0, MEM_STCFG3
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10000000
sw t1, 0(t0)
sync
j ra
nop
/*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}
/*
* (C) Copyright 2003
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
/* Define FPGA_DEBUG to get debug printf's */
/* #define FPGA_DEBUG */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#undef CFG_FPGA_CHECK_BUSY
#define CFG_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
* the board config file to slow things down.
*/
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CFG_FPGA_WAIT
#define CFG_FPGA_WAIT 100
#endif
static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
/* static int ACEX1K_ps_info( Altera_desc *desc ); */
static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
/* ------------------------------------------------------------------------- */
/* ACEX1K Generic Implementation */
int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
ret_val = ACEX1K_ps_load (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
ret_val = ACEX1K_ps_dump (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int ACEX1K_info( Altera_desc *desc )
{
return FPGA_SUCCESS;
}
int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (desc->family != Altera_ACEX1K) {
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
return FPGA_FAIL;
} else
switch (desc->iface) {
case passive_serial:
ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
/* ACEX1K Passive Serial Generic Implementation */
static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
int i;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"clk:\t0x%p\n"
"data:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
#ifdef CFG_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);