Commit 6069ff26 authored by wdenk's avatar wdenk

* Add support for 16 MB flash configuration of TRAB board

* Patch by Erwin Rol, 27 Feb 2003:
  Add support for RTEMS

* Add image information to README

* Fix dual PCMCIA slot support (when running with just one
  slot populated)

* Add VFD type detection to trab board

* extend drivers/cs8900.c driver to synchronize  ethaddr  environment
  variable with value in the EEPROM

* Start adding MIPS support files
parent 2a9e02ea
......@@ -2354,6 +2354,46 @@ format!) to the "bootm" command:
bash#
More About U-Boot Image Types:
------------------------------
U-Boot supports the following image types:
"Standalone Programs" are directly runnable in the environment
provided by U-Boot; it is expected that (if they behave
well) you can continue to work in U-Boot after return from
the Standalone Program.
"OS Kernel Images" are usually images of some Embedded OS which
will take over control completely. Usually these programs
will install their own set of exception handlers, device
drivers, set up the MMU, etc. - this means, that you cannot
expect to re-enter U-Boot except by resetting the CPU.
"RAMDisk Images" are more or less just data blocks, and their
parameters (address, size) are passed to an OS kernel that is
being started.
"Multi-File Images" contain several images, typically an OS
(Linux) kernel image and one or more data images like
RAMDisks. This construct is useful for instance when you want
to boot over the network using BOOTP etc., where the boot
server provides just a single image file, but you want to get
for instance an OS kernel and a RAMDisk image.
"Multi-File Images" start with a list of image sizes, each
image size (in bytes) specified by an "uint32_t" in network
byte order. This list is terminated by an "(uint32_t)0".
Immediately after the terminating 0 follow the images, one by
one, all aligned on "uint32_t" boundaries (size rounded up to
a multiple of 4 bytes).
"Firmware Images" are binary images containing firmware (like
U-Boot or FPGA images) which usually will be programmed to
flash memory.
"Script files" are command sequences that will be executed by
U-Boot's command interpreter; this feature is especially
useful when you configure U-Boot to use a real shell (hush)
as command interpreter.
Standalone HOWTO:
=================
......
......@@ -31,35 +31,35 @@
static void irq_init(void)
{
/* disable global interrupt mode */
write_mmcr_byte(SC520_PICICR, 0x40);
write_mmcr_byte(SC520_PICICR, 0x40);
/* set irq0-7 to edge */
write_mmcr_byte(SC520_MPICMODE, 0x00);
/* set irq9-12 to level, all the other (8, 13-15) are edge */
write_mmcr_byte(SC520_SL1PICMODE, 0x1e);
/* set irq16-24 (unused slave pic2) to level */
write_mmcr_byte(SC520_SL2PICMODE, 0xff);
/* active low polarity on PIC interrupt pins,
/* active low polarity on PIC interrupt pins,
active high polarity on all other irq pins */
write_mmcr_word(SC520_INTPINPOL, 0);
/* set irq number mapping */
write_mmcr_byte(SC520_GPTMR0MAP,0); /* disable GP timer 0 INT */
write_mmcr_byte(SC520_GPTMR0MAP,0); /* disable GP timer 0 INT */
write_mmcr_byte(SC520_GPTMR1MAP,0); /* disable GP timer 1 INT */
write_mmcr_byte(SC520_GPTMR2MAP,0); /* disable GP timer 2 INT */
write_mmcr_byte(SC520_PIT0MAP,0x1); /* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte(SC520_PIT0MAP,0x1); /* Set PIT timer 0 INT to IRQ0 */
write_mmcr_byte(SC520_PIT1MAP,0); /* diable PIT timer 1 INT */
write_mmcr_byte(SC520_PIT2MAP,0); /* diable PIT timer 2 INT */
write_mmcr_byte(SC520_PCIINTAMAP,0x4); /* Set PCI INT A to IRQ9 */
write_mmcr_byte(SC520_PCIINTBMAP,0x5); /* Set PCI INT B to IRQ10 */
write_mmcr_byte(SC520_PCIINTCMAP,0x6); /* Set PCI INT C to IRQ11 */
write_mmcr_byte(SC520_PCIINTDMAP,0x7); /* Set PCI INT D to IRQ12 */
write_mmcr_byte(SC520_DMABCINTMAP,0); /* disable DMA INT */
write_mmcr_byte(SC520_DMABCINTMAP,0); /* disable DMA INT */
write_mmcr_byte(SC520_SSIMAP,0); /* disable Synchronius serial INT */
write_mmcr_byte(SC520_WDTMAP,0); /* disable Watchdor INT */
write_mmcr_byte(SC520_RTCMAP,0x3); /* Set RTC int to 8 */
......@@ -69,28 +69,28 @@ static void irq_init(void)
write_mmcr_byte(SC520_GP0IMAP,6); /* Set GPIRQ0 (ISA IRQ2) to IRQ9 */
write_mmcr_byte(SC520_GP1IMAP,2); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
write_mmcr_byte(SC520_GP2IMAP,7); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
if (CFG_USE_SIO_UART) {
write_mmcr_byte(SC520_UART1MAP,0); /* disable internal UART1 INT */
write_mmcr_byte(SC520_UART2MAP,0); /* disable internal UART2 INT */
write_mmcr_byte(SC520_GP3IMAP,11); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
write_mmcr_byte(SC520_GP3IMAP,11); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
write_mmcr_byte(SC520_GP4IMAP,12); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
} else {
write_mmcr_byte(SC520_UART1MAP,12); /* Set internal UART2 INT to IRQ4 */
write_mmcr_byte(SC520_UART2MAP,11); /* Set internal UART2 INT to IRQ3 */
write_mmcr_byte(SC520_GP3IMAP,0); /* disable GPIRQ3 (ISA IRQ3) */
write_mmcr_byte(SC520_GP3IMAP,0); /* disable GPIRQ3 (ISA IRQ3) */
write_mmcr_byte(SC520_GP4IMAP,0); /* disable GPIRQ4 (ISA IRQ4) */
}
write_mmcr_byte(SC520_GP5IMAP,13); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
write_mmcr_byte(SC520_GP6IMAP,21); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
write_mmcr_byte(SC520_GP7IMAP,22); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
write_mmcr_byte(SC520_GP8IMAP,3); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
write_mmcr_byte(SC520_GP9IMAP,4); /* Set GPIRQ9 (ISA IRQ9) to IRQ9 */
write_mmcr_byte(SC520_GP10IMAP,9); /* Set GPIRQ10 (ISA IRQ10) to IRQ10 */
write_mmcr_byte(SC520_GP10IMAP,9); /* Set GPIRQ10 (ISA IRQ10) to IRQ10 */
write_mmcr_word(SC520_PCIHOSTMAP,0x11f); /* Map PCI hostbridge INT to NMI */
write_mmcr_word(SC520_ECCMAP,0x100); /* Map SDRAM ECC failure INT to NMI */
}
/* PCI stuff */
......@@ -98,11 +98,11 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
char pin;
int irq;
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
irq = pin-1;
switch (PCI_DEV(dev)) {
case 20:
break;
......@@ -115,20 +115,20 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
case 17:
irq+=3;
break;
default:
default:
return;
}
irq&=3; /* wrap around */
irq+=9; /* lowest IRQ is 9 */
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, irq);
#if 0
printf("fixup_irq: device %d pin %c irq %d\n",
#if 0
printf("fixup_irq: device %d pin %c irq %d\n",
PCI_DEV(dev), 'A' + pin -1, irq);
#endif
}
static struct pci_controller sc520_cdp_hose = {
fixup_irq: pci_sc520_cdp_fixup_irq,
};
......@@ -147,7 +147,7 @@ static void silence_uart(int port)
void setup_ali_sio(int uart_primary)
{
ali512x_init();
ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
......@@ -155,21 +155,21 @@ void setup_ali_sio(int uart_primary)
ali512x_set_rtc(ALI_DISABLED, 0, 0);
ali512x_set_kbc(ALI_ENABLED, 1, 12);
ali512x_set_cio(ALI_ENABLED);
/* IrDa pins */
ali512x_cio_function(12, 1, 0, 0);
ali512x_cio_function(13, 1, 0, 0);
/* SSI chip select pins */
ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
ali512x_cio_function(16, 0, 1, 0); /* SSI_SPI# (inverted) */
/* Board REV pins */
ali512x_cio_function(20, 0, 0, 1);
ali512x_cio_function(21, 0, 0, 1);
ali512x_cio_function(22, 0, 0, 1);
ali512x_cio_function(23, 0, 0, 1);
ali512x_cio_function(23, 0, 0, 1);
}
......@@ -178,13 +178,13 @@ static void bus_init(void)
{
/* set up the GP IO pins */
write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
write_mmcr_byte(SC520_CLKSEL, 0x70);
write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
......@@ -192,40 +192,40 @@ static void bus_init(void)
write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
* and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
/* SRAM = GPCS3 128k @ d0000-effff*/
write_mmcr_long(SC520_PAR2, 0x4e00400d);
write_mmcr_long(SC520_PAR2, 0x4e00400d);
/* IDE0 = GPCS6 1f0-1f7 */
write_mmcr_long(SC520_PAR3, 0x380801f0);
write_mmcr_long(SC520_PAR3, 0x380801f0);
/* IDE1 = GPCS7 3f6 */
write_mmcr_long(SC520_PAR4, 0x3c0003f6);
write_mmcr_long(SC520_PAR4, 0x3c0003f6);
/* bootcs */
write_mmcr_long(SC520_PAR12, 0x8bffe800);
write_mmcr_long(SC520_PAR12, 0x8bffe800);
/* romcs2 */
write_mmcr_long(SC520_PAR13, 0xcbfff000);
write_mmcr_long(SC520_PAR13, 0xcbfff000);
/* romcs1 */
write_mmcr_long(SC520_PAR14, 0xabfff800);
write_mmcr_long(SC520_PAR14, 0xabfff800);
/* 680 LEDS */
write_mmcr_long(SC520_PAR15, 0x30000640);
asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
write_mmcr_long(SC520_PAR15, 0x30000640);
asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
if (CFG_USE_SIO_UART) {
write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
setup_ali_sio(1);
} else {
write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
setup_ali_sio(0);
silence_uart(0x3e8);
silence_uart(0x2e8);
......@@ -242,21 +242,21 @@ static void bus_init(void)
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
init_sc520();
init_sc520();
bus_init();
irq_init();
/* max drive current on SDRAM */
write_mmcr_word(SC520_DSCTL, 0x0100);
/* enter debug mode after next reset (only if jumper is also set) */
write_mmcr_byte(SC520_RESCFG, 0x08);
/* configure the software timer to 33.333MHz */
write_mmcr_byte(SC520_SWTMRCFG, 0);
gd->bus_clk = 33333000;
return 0;
}
......@@ -277,14 +277,14 @@ int last_stage_init(void)
{
int minor;
int major;
major = minor = 0;
major |= ali512x_cio_in(23)?2:0;
major |= ali512x_cio_in(22)?1:0;
minor |= ali512x_cio_in(21)?2:0;
minor |= ali512x_cio_in(20)?1:0;
printf("AMD SC520 CDP revision %d.%d\n", major, minor);
return 0;
}
......@@ -76,7 +76,7 @@ ulong flash_init (void)
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
flashbase = CFG_FLASH_BASE;
else
panic ("configured too many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
......
......@@ -26,12 +26,7 @@
#include <common.h>
#include <environment.h>
ulong myflush (void);
#define FLASH_BANK_SIZE 0x800000 /* 8 MB */
/* this varies depending on the sector */
#define MAIN_SECT_SIZE 0x20000 /* 2 x 64 kB */
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
......@@ -43,6 +38,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define CMD_ERASE_CONFIRM 0x00300030
#define CMD_PROGRAM 0x00A000A0
#define CMD_UNLOCK_BYPASS 0x00200020
#define CMD_READ_MANF_ID 0x00900090
#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
......@@ -64,27 +60,38 @@ ulong flash_init (void)
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
ulong flashbase = 0;
flash_info_t *info = &flash_info[i];
/* Init: no FLASHes known */
info->flash_id = FLASH_UNKNOWN;
size += flash_get_size (CFG_FLASH_BASE, info);
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV320B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
flashbase = CFG_FLASH_BASE;
else
panic ("configured too many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = flashbase;
/* the first 8 sectors are 8 kB */
flashbase += (j < 8) ? 0x4000 : MAIN_SECT_SIZE;
for (j = 0; j < info->sector_count; j++) {
info->protect[j] = 0;
info->start[j] = flashbase;
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_AM320B & FLASH_TYPEMASK):
/* Boot sector type: 8 x 8 + N x 128 kB */
flashbase += (j < 8) ? 0x4000 : 0x20000;
break;
case (FLASH_AM640U & FLASH_TYPEMASK):
/* Uniform sector type: 128 kB */
flashbase += 0x20000;
break;
default:
printf ("## Bad flash chip type 0x%04lX\n",
info->flash_id & FLASH_TYPEMASK);
}
}
size += flash_info[i].size;
}
/*
......@@ -116,7 +123,7 @@ void flash_print_info (flash_info_t * info)
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
case (FLASH_MAN_AMD & FLASH_VENDMASK):
printf ("AMD: ");
break;
default:
......@@ -125,9 +132,12 @@ void flash_print_info (flash_info_t * info)
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV320B & FLASH_TYPEMASK):
case (FLASH_AM320B & FLASH_TYPEMASK):
printf ("2x Am29LV320DB (32Mbit)\n");
break;
case (FLASH_AM640U & FLASH_TYPEMASK):
printf ("2x Am29LV640D (64Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
......@@ -177,7 +187,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
(FLASH_MAN_AMD & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
......@@ -265,13 +275,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
rc = ERR_TIMOUT;
goto outahere;
}
#if 0
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
#endif
}
}
......@@ -453,3 +456,71 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
return write_word (info, wp, data);
}
/*-----------------------------------------------------------------------
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
ulong value;
/* Write auto select command sequence and read Manufacturer ID */
addr[0x0555] = CMD_UNLOCK1;
addr[0x02AA] = CMD_UNLOCK2;
addr[0x0555] = CMD_READ_MANF_ID;
value = addr[0];
debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
switch (value) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = 0x00FF00FF; /* restore read mode */
debug ("## flash_init: unknown manufacturer\n");
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
switch (value) {
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00800000;
addr[0] = 0x00FF00FF; /* restore read mode */
break; /* => 8 MB */
case AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x01000000;
addr[0] = 0x00F000F0; /* restore read mode */
break; /* => 16 MB */
default:
debug ("## flash_init: unknown flash chip\n");
info->flash_id = FLASH_UNKNOWN;
addr[0] = 0x00FF00FF; /* restore read mode */
return (0); /* => no or unknown flash */
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
}
return (info->size);
}
......@@ -60,11 +60,8 @@ static void udelay_no_timer (int usec)
int board_init ()
{
#if defined(CONFIG_MODEM_SUPPORT) && defined(CONFIG_VFD)
ulong size;
unsigned long addr;
extern void mem_malloc_init (ulong);
extern int drv_vfd_init(void);
#if defined(CONFIG_VFD)
extern int vfd_init_clocks(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
......@@ -107,26 +104,11 @@ int board_init ()
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0c000100;
#ifdef CONFIG_MODEM_SUPPORT
#ifdef CONFIG_VFD
#ifndef PAGE_SIZE
#define PAGE_SIZE 4096
#endif
/*
* reserve memory for VFD display (always full pages)
*/
/* armboot_real_end is defined in the board-specific linker script */
addr = (_armboot_real_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
size = vfd_setmem (addr);
gd->fb_base = addr;
/* round to the next page boundary */
addr += size;
addr = (addr + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
mem_malloc_init (addr);
/* must do this after the framebuffer is allocated */
drv_vfd_init();
vfd_init_clocks();
#endif /* CONFIG_VFD */
#ifdef CONFIG_MODEM_SUPPORT
udelay_no_timer (KBD_MDELAY);
if (key_pressed()) {
......
This diff is collapsed.
......@@ -192,6 +192,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (hdr->ih_arch != IH_CPU_ARM)
#elif defined(__I386__)
if (hdr->ih_arch != IH_CPU_I386)
#elif defined(__mips__)
if (hdr->ih_arch != IH_CPU_MIPS)
#else
# error Unknown CPU type
#endif
......
......@@ -252,11 +252,13 @@ int valid_elf_image (unsigned long addr)
return 0;
}
#if 0
if (ehdr->e_machine != EM_PPC) {
printf ("## Not a PowerPC elf image at address 0x%08lx\n",
addr);
return 0;
}
#endif
return 1;
}
......
......@@ -489,11 +489,14 @@ void ide_init (void)
#ifdef CONFIG_IDE_8xx_PCCARD
extern int pcmcia_on (void);
extern int ide_devices_found; /* Initialized in check_ide_device() */
WATCHDOG_RESET();
ide_devices_found = 0;
/* initialize the PCMCIA IDE adapter card */
if (pcmcia_on())
pcmcia_on();
if (!ide_devices_found)
return;
udelay (1000000); /* 1 s */
#endif /* CONFIG_IDE_8xx_PCCARD */
......@@ -550,6 +553,13 @@ void ide_init (void)
int dev = bus * (CFG_IDE_MAXDEVICE / max_bus_scan);
#endif
#ifdef CONFIG_IDE_8xx_PCCARD
/* Skip non-ide devices from probing */
if ((ide_devices_found & (1 << bus)) == 0) {
ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */
continue;
}
#endif
printf ("Bus %d: ", bus);
ide_bus_ok[bus] = 0;
......
......@@ -268,6 +268,7 @@ static int pcmcia_off (void)
#define MAX_TUPEL_SZ 512
#define MAX_FEATURES 4
int ide_devices_found;
static int check_ide_device (int slot)
{
volatile uchar *ident = NULL;
......@@ -347,6 +348,8 @@ static int check_ide_device (int slot)
return (1);
}
ide_devices_found |= (1 << slot);
/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
*((uchar *)(addr + config_base)) = 1;
......
......@@ -28,12 +28,13 @@ include $(TOPDIR)/config.mk
LIB = libdrivers.a
OBJS = 3c589.o 5701rls.o bcm570x.o bcm570x_autoneg.o \
cfb_console.o cs8900.o dc2114x.o eepro100.o \
i8042.o natsemi.o ns16550.o ns8382x.o ns87308.o \
cfb_console.o cs8900.o ct69000.o dc2114x.o \
eepro100.o i8042.o inca-ip_sw.o \
natsemi.o ns16550.o ns8382x.o ns87308.o \
pci.o pci_auto.o pci_indirect.o \
pcnet.o sed13806.o serial.o \
smc91111.o smiLynxEM.o sym53c8xx.o \
tigon3.o w83c553f.o ct69000.o
tigon3.o w83c553f.o
all: $(LIB)
......
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......@@ -11,7 +11,6 @@
/* History: */
/******************************************************************************/
#include <common.h>
#include "bcm570x_mm.h"
#include <asm/types.h>
#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \
defined(CONFIG_TIGON3)
......@@ -20,6 +19,7 @@
#endif
#include <malloc.h>
#include <linux/byteorder/big_endian.h>
#include "bcm570x_mm.h"
#define EMBEDDED 1
/******************************************************************************/
......
......@@ -27,6 +27,10 @@ include $(TOPDIR)/config.mk
SREC = hello_world.srec
ifeq ($(CPU),mips)
SREC =
endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
SREC += timer.srec
......
......@@ -37,7 +37,37 @@ mon_free:
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
ldmea fp, {fp, sp, pc}
#else /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
#elif defined(CONFIG_MIPS)/* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
#warning MIPS version not implemented yet
.global mon_getc
.type mon_getc,function
mon_getc:
.global mon_tstc
.type mon_tstc,function
mon_tstc:
.global mon_putc
.type mon_putc,function
mon_putc:
.global mon_puts
.type mon_puts,function
mon_puts:
.global mon_printf
.type mon_printf,function
mon_printf:
.global mon_install_hdlr
.type mon_install_hdlr,function
mon_install_hdlr:
.global mon_free_hdlr
.type mon_free_hdlr,function
mon_free_hdlr:
.global mon_malloc
.type mon_malloc,function
mon_malloc:
.global mon_free
.type mon_free,function
mon_free:
#else
#ifdef CONFIG_I386 /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
#define SYMBOL_NAME(X) X
......
......@@ -43,6 +43,8 @@ typedef struct global_data {
unsigned long env_valid; /* Checksum of Environment valid? */
#ifdef CONFIG_VFD
unsigned long fb_base; /* base address of frame buffer */
unsigned char vfd_type; /* display type */
unsigned char vfd_inv_data; /* inverted data lines ? */
#endif
#if 0
unsigned long cpu_clk; /* CPU clock in Hz! */
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 by Ralf Baechle