Commit 6297872c authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-arm

parents 0ae39166 f04c5376
......@@ -144,7 +144,6 @@ Directory Hierarchy:
/arm1136 Files specific to ARM 1136 CPUs
/ixp Files specific to Intel XScale IXP CPUs
/pxa Files specific to Intel XScale PXA CPUs
/s3c44b0 Files specific to Samsung S3C44B0 CPUs
/sa1100 Files specific to Intel StrongARM SA1100 CPUs
/lib Architecture specific library files
/avr32 Files generic to AVR32 architecture
......@@ -5598,15 +5597,17 @@ On ARM, the following registers are used:
R0: function argument word/integer result
R1-R3: function argument word
R9: GOT pointer
R10: stack limit (used only if stack checking if enabled)
R9: platform specific
R10: stack limit (used only if stack checking is enabled)
R11: argument (frame) pointer
R12: temporary workspace
R13: stack pointer
R14: link register
R15: program counter
==> U-Boot will use R8 to hold a pointer to the global data
==> U-Boot will use R9 to hold a pointer to the global data
Note: on ARM, only R_ARM_RELATIVE relocations are supported.
On Nios II, the ABI is documented here:
http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
......
......@@ -16,7 +16,8 @@ endif
endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9 -msoft-float
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
......@@ -94,7 +95,11 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
endif
endif
# check that only R_ARM_RELATIVE relocations are generated
ifneq ($(CONFIG_SPL_BUILD),y)
ALL-y += checkarmreloc
# Check that only R_ARM_RELATIVE relocations are generated.
ALL-y += checkarmreloc
# The movt / movw can hardcode 16 bit parts of the addresses in the
# instruction. Relocation is not supported for that case, so disable
# such usage by requiring word relocations.
PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
endif
......@@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5
......
......@@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5t
......
......@@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
# =========================================================================
#
......
......@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
......
......@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
......
......@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv5te
# =========================================================================
#
......
......@@ -38,5 +38,10 @@ int main(void)
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, gpcr));
DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, fmcr));
return 0;
}
......@@ -102,8 +102,9 @@ static uint8_t mxs_get_bootmode_index(void)
return i;
}
void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
......
This diff is collapsed.
......@@ -152,39 +152,49 @@ _reset:
/*
* Store all registers on old stack pointer, this will allow us later to
* return to the BootROM and let the BootROM load U-Boot into RAM.
*
* WARNING: Register r0 and r1 are used by the BootROM to pass data
* to the called code. Register r0 will contain arbitrary
* data that are set in the BootStream. In case this code
* was started with CALL instruction, register r1 will contain
* pointer to the return value this function can then set.
* The code below MUST NOT CHANGE register r0 and r1 !
*/
push {r0-r12,r14}
/* save control register c1 */
mrc p15, 0, r0, c1, c0, 0
push {r0}
/* Save control register c1 */
mrc p15, 0, r2, c1, c0, 0
push {r2}
/*
* set the cpu to SVC32 mode and store old CPSR register content
*/
mrs r0,cpsr
push {r0}
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/* Set the cpu to SVC32 mode and store old CPSR register content. */
mrs r2, cpsr
push {r2}
bic r2, r2, #0x1f
orr r2, r2, #0xd3
msr cpsr, r2
bl board_init_ll
/* Restore BootROM's CPU mode (especially FIQ). */
pop {r2}
msr cpsr,r2
/*
* restore bootrom's cpu mode (especially FIQ)
* Restore c1 register. Especially set exception vector location
* back to BootROM space which is required by bootrom for USB boot.
*/
pop {r0}
msr cpsr,r0
pop {r2}
mcr p15, 0, r2, c1, c0, 0
pop {r0-r12,r14}
/*
* restore c1 register
* (especially set exception vector location back to
* bootrom space which is required by bootrom for USB boot)
* In case this code was started by the CALL instruction, the register
* r0 is examined by the BootROM after this code returns. The value in
* r0 must be set to 0 to indicate successful return.
*/
pop {r0}
mcr p15, 0, r0, c1, c0, 0
mov r0, #0
pop {r0-r12,r14}
bx lr
_hang:
......
......@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
......
......@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
......
......@@ -27,6 +27,7 @@
#include <miiphy.h>
#include <cpsw.h>
#include <asm/errno.h>
#include <linux/compiler.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
......@@ -137,6 +138,16 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
*/
__weak void am33xx_spl_board_init(void)
{
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
......
......@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
.cm_div_m2_dpll = CM_WKUP + 0xA0,
};
const struct dpll_params dpll_mpu = {
struct dpll_params dpll_mpu_opp100 = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
const struct dpll_params dpll_core_opp100 = {
1000, OSC-1, -1, -1, 10, 8, 4};
const struct dpll_params dpll_mpu = {
MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
50, OSC-1, -1, -1, 1, 1, 1};
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};
......
......@@ -17,6 +17,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
......@@ -119,3 +120,59 @@ int print_cpuinfo(void)
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#ifdef CONFIG_AM33XX
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
{
int sil_rev;
sil_rev = readl(&cdev->deviceid) >> 28;
if (sil_rev == 1)
/* PG 2.0, efuse may not be set. */
return MPUPLL_M_800;
else if (sil_rev >= 2) {
/* Check what the efuse says our max speed is. */
int efuse_arm_mpu_max_freq;
efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
case AM335X_ZCZ_1000:
return MPUPLL_M_1000;
case AM335X_ZCZ_800:
return MPUPLL_M_800;
case AM335X_ZCZ_720:
return MPUPLL_M_720;
case AM335X_ZCZ_600:
case AM335X_ZCE_600:
return MPUPLL_M_600;
case AM335X_ZCZ_300:
case AM335X_ZCE_300:
return MPUPLL_M_300;
}
}
/* PG 1.0 or otherwise unknown, use the PG1.0 max */
return MPUPLL_M_720;
}
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
/* For PG2.1 and later, we have one set of values. */
if (sil_rev >= 2) {
switch (frequency) {
case MPUPLL_M_1000:
return TPS65910_OP_REG_SEL_1_3_2_5;
case MPUPLL_M_800:
return TPS65910_OP_REG_SEL_1_2_6;
case MPUPLL_M_720:
return TPS65910_OP_REG_SEL_1_2_0;
case MPUPLL_M_600:
case MPUPLL_M_300:
return TPS65910_OP_REG_SEL_1_1_3;
}
}
/* Default to PG1.0/PG2.0 values. */
return TPS65910_OP_REG_SEL_1_1_3;
}
#endif
......@@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# If armv7-a is not supported by GCC fall-back to armv5, which is
# supported by more tool-chains
......
......@@ -22,11 +22,11 @@ ENTRY(lowlevel_init)
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_BUILD
ldr r8, =gdata
ldr r9, =gdata
#else
sub sp, #GD_SIZE
bic sp, sp, #7
mov r8, sp
mov r9, sp
#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
......
......@@ -228,13 +228,13 @@ static u32 get_axi_clk(void)
static u32 get_emi_slow_clk(void)
{
u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
cscmr1 = __raw_readl(&imx_ccm->cscmr1);
emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
switch (emi_clk_sel) {
case 0:
......@@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void)
break;
}
return root_freq / (emi_slow_pof + 1);
return root_freq / (emi_slow_podf + 1);
}
#ifdef CONFIG_MX6SL
......@@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void)
return freq / (podf + 1);
}
int enable_fec_anatop_clock(void)
{
u32 reg = 0;
s32 timeout = 100000;
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
reg = readl(&anatop->pll_enet);
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
writel(reg, &anatop->pll_enet);
while (timeout--) {
if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
break;
}
if (timeout < 0)
return -ETIMEDOUT;
}
/* Enable FEC clock */
reg |= BM_ANADIG_PLL_ENET_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);
return 0;
}
#else
static u32 get_mmdc_ch0_clk(void)
{
......@@ -457,7 +487,7 @@ void enable_ipu_clock(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
/***************************************************/
......
......@@ -76,6 +76,9 @@ void spl_board_init(void)
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
}
int board_mmc_init(bd_t *bis)
......
......@@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
val = optimize_vcore_voltage(&vcores->iva);
do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, (*prcm)->prm_sldo_core_setup);
writel(2, (*prcm)->prm_sldo_mpu_setup);
writel(2, (*prcm)->prm_sldo_mm_setup);
}
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
......
......@@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
.prm_sldo_core_setup = 0x4ae07bc4,
.prm_sldo_core_ctrl = 0x4ae07bc8,
.prm_sldo_mpu_setup = 0x4ae07bcc,
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
/* SCRM stuff, used by some boards */
.scrm_auxclk0 = 0x4ae0a310,
......@@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
.prm_sldo_core_setup = 0x4ae07cc4,
.prm_sldo_core_ctrl = 0x4ae07cc8,
.prm_sldo_mpu_setup = 0x4ae07ccc,
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
.prm_abbldo_mpu_setup = 0x4ae07cdc,
.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
......
......@@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5
......@@ -57,7 +57,7 @@ int timer_init(void)
SCUTIMER_CONTROL_ENABLE_MASK;
/* Load the timer counter register */
writel(0xFFFFFFFF, &timer_base->counter);
writel(0xFFFFFFFF, &timer_base->load);
/*
* Start the A9Timer device
......
......@@ -8,7 +8,7 @@
BIG_ENDIAN = y
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
PLATFORM_RELFLAGS += -mbig-endian
PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
......
......@@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -mcpu=xscale
# =========================================================================
#
......
/*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/hardware.h>
static void s3c44b0_flush_cache(void)
{
volatile int i;
/* flush cycle */
for(i=0x10002000;i<0x10004800;i+=16)
{
*((int *)i)=0x0;
}
}
void icache_enable (void)
{
ulong reg;
s3c44b0_flush_cache();
/*
Init cache
Non-cacheable area (everything outside RAM)
0x0000:0000 - 0x0C00:0000
*/
NCACHBE0 = 0xC0000000;
NCACHBE1 = 0x00000000;
/*
Enable chache
*/
reg = SYSCFG;
reg |= 0x00000006; /* 8kB */
SYSCFG = reg;
}
void icache_disable (void)
{
ulong reg;
reg = SYSCFG;
reg &= ~0x00000006; /* 8kB */
SYSCFG = reg;
}
int icache_status (void)
{
return 0;
}
void dcache_enable (void)
{
icache_enable();
}
void dcache_disable (void)
{
icache_disable();
}
int dcache_status (void)
{
return dcache_status();
}
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
# =========================================================================
#
# Supply options according to compiler version
#
# ========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
/*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* S3C44B0 CPU specific code
*/
#include <common.h>
#include <command.h>
#include <asm/hardware.h>
int arch_cpu_init (void)
{
icache_enable();
return 0;
}
int cleanup_before_linux (void)
{
/*
cache memory should be enabled before calling
Linux to make the kernel uncompression faster
*/
icache_enable();
disable_interrupts ();
return 0;
}
void reset_cpu (ulong addr)
{
/*
reset the cpu using watchdog
*/
/* Disable the watchdog.*/
WTCON&=~(1<<5);
/* set the timeout value to a short time... */
WTCNT = 0x1;
/* Enable the watchdog. */
WTCON|=1;
WTCON|=(1<<5);
while(1) {
/*NOP*/
}
}
/*
* Startup Code for S3C44B0 CPU-core
*
* (C) Copyright 2004
* DAVE Srl
*
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
* Jump vector table
*/