Commit 682011ff authored by wdenk's avatar wdenk

* Patches by Udi Finkelstein, 2 June 2003:

  - Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonnire, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration
parent 7a8e9bed
...@@ -2,6 +2,27 @@ ...@@ -2,6 +2,27 @@
Changes since U-Boot 0.3.1: Changes since U-Boot 0.3.1:
====================================================================== ======================================================================
* Patches by Udi Finkelstein, 2 June 2003:
- Added support for custom keyboards, initialized by defining a
board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- Added support for the RBC823 board.
- cpu/mpc8xx/lcd.c now automatically calculates the
Horizontal Pixel Count field.
* Fix alignment problem in BOOTP (dhcp_leasetime option)
[pointed out by Nicolas Lacressonnire, 2 Jun 2003]
* Patch by Mark Rakes, 14 May 2003:
add support for Intel e1000 gig cards.
* Patch by Nye Liu, 3 Jun 2003:
fix critical typo in MAMR definition (include/mpc8xx.h)
* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
* Patch by Klaus Heydeck, 2 Jun 2003
Minor changes for KUP4K configuration
* Patch by Marc Singer, 29 May 2003: * Patch by Marc Singer, 29 May 2003:
Fixed rarp boot method for IA32 and other little-endian CPUs. Fixed rarp boot method for IA32 and other little-endian CPUs.
......
...@@ -32,11 +32,11 @@ LIST_8xx=" \ ...@@ -32,11 +32,11 @@ LIST_8xx=" \
IVMS8 IVMS8_128 IVMS8_256 KUP4K \ IVMS8 IVMS8_128 IVMS8_256 KUP4K \
LANTEC lwmon MBX MBX860T \ LANTEC lwmon MBX MBX860T \
MHPC MVS1 NETVIA NX823 \ MHPC MVS1 NETVIA NX823 \
pcu_e R360MPI RPXClassic RPXlite \ pcu_e R360MPI RBC823 RPXClassic \
RRvision SM850 SPD823TS svm_sc8xx \ RPXlite RRvision SM850 SPD823TS \
SXNI855T TOP860 TQM823L TQM823L_LCD \ svm_sc8xx SXNI855T TOP860 TQM823L \
TQM850L TQM855L TQM860L TTTech \ TQM823L_LCD TQM850L TQM855L TQM860L \
v37 \ TTTech v37 \
" "
######################################################################### #########################################################################
......
...@@ -314,6 +314,9 @@ pcu_e_config: unconfig ...@@ -314,6 +314,9 @@ pcu_e_config: unconfig
R360MPI_config: unconfig R360MPI_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx r360mpi @./mkconfig $(@:_config=) ppc mpc8xx r360mpi
RBC823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx rbc823
RPXClassic_config: unconfig RPXClassic_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx RPXClassic @./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
......
...@@ -344,7 +344,7 @@ The following options need to be configured: ...@@ -344,7 +344,7 @@ The following options need to be configured:
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L, CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI, CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA CONFIG_NETVIA, CONFIG_RBC823
ARM based boards: ARM based boards:
----------------- -----------------
...@@ -688,6 +688,9 @@ The following options need to be configured: ...@@ -688,6 +688,9 @@ The following options need to be configured:
CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
- NETWORK Support (PCI): - NETWORK Support (PCI):
CONFIG_E1000
Support for Intel 8254x gigabit chips.
CONFIG_EEPRO100 CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips. Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
...@@ -766,6 +769,13 @@ The following options need to be configured: ...@@ -766,6 +769,13 @@ The following options need to be configured:
and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
or CONFIG_VIDEO_SED13806_16BPP or CONFIG_VIDEO_SED13806_16BPP
- Keyboard Support:
CONFIG_KEYBOARD
Define this to enable a custom keyboard support.
This simply calls drv_keyboard_init() which must be
defined in your board-specific files.
The only board using this so far is RBC823.
- LCD Support: CONFIG_LCD - LCD Support: CONFIG_LCD
......
...@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) ...@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = value|(value<<16); value = value|(value<<16);
switch (value) { switch (value) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT: case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ; info->flash_id = FLASH_MAN_FUJ;
break; break;
...@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) ...@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 19; info->sector_count = 19;
info->size = 0x00100000; info->size = 0x00100000;
break; /* => 1 MB */ break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
default: default:
info->flash_id = FLASH_UNKNOWN; info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */ return (0); /* => no or unknown flash */
......
This diff is collapsed.
...@@ -50,66 +50,64 @@ typedef struct ...@@ -50,66 +50,64 @@ typedef struct
static S1D_REGS aS1DRegs[] = static S1D_REGS aS1DRegs[] =
{ {
{0x04,0x10}, /* BUSCLK MEMCLK Config Register */
{0x04,0x10}, /* BUSCLK MEMCLK Config Register */
#if 0 #if 0
{0x05,0x32}, /* PCLK Config Register */ {0x05,0x32}, /* PCLK Config Register */
#endif #endif
{0x10,0xD0}, /* PANEL Type Register */ {0x10,0xD0}, /* PANEL Type Register */
{0x11,0x00}, /* MOD Rate Register */ {0x11,0x00}, /* MOD Rate Register */
#if 0 #if 0
{0x12,0x34}, /* Horizontal Total Register */ {0x12,0x34}, /* Horizontal Total Register */
#endif #endif
{0x14,0x27}, /* Horizontal Display Period Register */ {0x14,0x27}, /* Horizontal Display Period Register */
{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
{0x18,0xF0}, /* Vertical Total Register 0 */ {0x18,0xF0}, /* Vertical Total Register 0 */
{0x19,0x00}, /* Vertical Total Register 1 */ {0x19,0x00}, /* Vertical Total Register 1 */
{0x1C,0xEF}, /* Vertical Display Period Register 0 */ {0x1C,0xEF}, /* Vertical Display Period Register 0 */
{0x1D,0x00}, /* Vertical Display Period Register 1 */ {0x1D,0x00}, /* Vertical Display Period Register 1 */
{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
{0x20,0x87}, /* Horizontal Sync Pulse Width Register */ {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
{0x24,0x80}, /* Vertical Sync Pulse Width Register */ {0x24,0x80}, /* Vertical Sync Pulse Width Register */
{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
{0x70,0x83}, /* Display Mode Register */ {0x70,0x83}, /* Display Mode Register */
{0x71,0x00}, /* Special Effects Register */ {0x71,0x00}, /* Special Effects Register */
{0x74,0x00}, /* Main Window Display Start Address Register 0 */ {0x74,0x00}, /* Main Window Display Start Address Register 0 */
{0x75,0x00}, /* Main Window Display Start Address Register 1 */ {0x75,0x00}, /* Main Window Display Start Address Register 1 */
{0x76,0x00}, /* Main Window Display Start Address Register 2 */ {0x76,0x00}, /* Main Window Display Start Address Register 2 */
{0x78,0x50}, /* Main Window Address Offset Register 0 */ {0x78,0x50}, /* Main Window Address Offset Register 0 */
{0x79,0x00}, /* Main Window Address Offset Register 1 */ {0x79,0x00}, /* Main Window Address Offset Register 1 */
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
{0x80,0x50}, /* Sub Window Address Offset Register 0 */ {0x80,0x50}, /* Sub Window Address Offset Register 0 */
{0x81,0x00}, /* Sub Window Address Offset Register 1 */ {0x81,0x00}, /* Sub Window Address Offset Register 1 */
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */ {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */ {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */ {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */ {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
{0xA0,0x00}, /* Power Save Config Register */ {0xA0,0x00}, /* Power Save Config Register */
{0xA1,0x00}, /* CPU Access Control Register */ {0xA1,0x00}, /* CPU Access Control Register */
{0xA2,0x00}, /* Software Reset Register */ {0xA2,0x00}, /* Software Reset Register */
{0xA3,0x00}, /* BIG Endian Support Register */ {0xA3,0x00}, /* BIG Endian Support Register */
{0xA4,0x00}, /* Scratch Pad Register 0 */ {0xA4,0x00}, /* Scratch Pad Register 0 */
{0xA5,0x00}, /* Scratch Pad Register 1 */ {0xA5,0x00}, /* Scratch Pad Register 1 */
{0xA8,0x01}, /* GPIO Config Register 0 */ {0xA8,0x01}, /* GPIO Config Register 0 */
{0xA9,0x80}, /* GPIO Config Register 1 */ {0xA9,0x80}, /* GPIO Config Register 1 */
{0xAC,0x01}, /* GPIO Status Control Register 0 */ {0xAC,0x01}, /* GPIO Status Control Register 0 */
{0xAD,0x00}, /* GPIO Status Control Register 1 */ {0xAD,0x00}, /* GPIO Status Control Register 1 */
{0xB0,0x00}, /* PWM CV Clock Control Register */ {0xB0,0x10}, /* PWM CV Clock Control Register */
{0xB1,0x00}, /* PWM CV Clock Config Register */ {0xB1,0x80}, /* PWM CV Clock Config Register */
{0xB2,0x00}, /* CV Clock Burst Length Register */ {0xB2,0x00}, /* CV Clock Burst Length Register */
{0xB3,0x00}, /* PWM Clock Duty Cycle Register */ {0xB3,0xA0}, /* PWM Clock Duty Cycle Register */
{0xAD,0x80}, /* reset seq */ {0xAD,0x80}, /* reset seq */
{0x70,0x03}, /* */ {0x70,0x03}, /* */
}; };
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o kbd.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# RBC823 boards
#
TEXT_BASE = 0xFFF00000
This diff is collapsed.
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Modified by Udi Finkelstein
*
* This file includes communication routines for SMC1 that can run even if
* SMC2 have already been initialized.
*/
#include <common.h>
#include <watchdog.h>
#include <commproc.h>
#include <devices.h>
#include <lcd.h>
#define SMC_INDEX 0
#define PROFF_SMC PROFF_SMC1
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
#define RBC823_KBD_BAUDRATE 38400
#define CPM_KEYBOARD_BASE 0x1000
/*
* Minimal serial functions needed to use one of the SMC ports
* as serial console interface.
*/
void smc1_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
*
* Wire BRG2 to SMC1, BRG1 to SMC2
*/
cp->cp_simode = 0x00001000;
cp->cp_brgc2 =
(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
}
int smc1_init (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
uint dpaddr;
/* initialize pointers to SMC */
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
/* Disable transmitter/receiver.
*/
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
/* Enable SDMA.
*/
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
#ifdef CFG_SDSR
im->im_sdma.sdma_sdsr = CFG_SDSR;
#else
im->im_sdma.sdma_sdsr = 0x83;
#endif
/* clear SDMA interrupt mask */
#ifdef CFG_SDMR
im->im_sdma.sdma_sdmr = CFG_SDMR;
#else
im->im_sdma.sdma_sdmr = 0x00;
#endif
/* Use Port B for SMC1 instead of other functions.
*/
cp->cp_pbpar |= 0x000000c0;
cp->cp_pbdir &= ~0x000000c0;
cp->cp_pbodr &= ~0x000000c0;
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
#ifdef CFG_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_KEYBOARD_BASE ;
#endif
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = 0;
tbdf = rbdf + 1;
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
/* Set up the uart parameters in the parameter ram.
*/
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
/* Mask all interrupts and remove anything pending.
*/
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
/* Set up the baud rate generator.
*/
smc1_setbrg ();
/* Make the first buffer the only buffer.
*/
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
/* Single character receive.
*/
up->smc_mrblr = 1;
up->smc_maxidl = 0;
/* Initialize Tx/Rx parameters.
*/
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
/* Enable transmitter/receiver.
*/
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
return (0);
}
void smc1_putc(const char c)
{
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
/* Wait for last character to go.
*/
buf = (char *)tbdf->cbd_bufaddr;
*buf = c;
tbdf->cbd_datlen = 1;
tbdf->cbd_sc |= BD_SC_READY;
__asm__("eieio");
while (tbdf->cbd_sc & BD_SC_READY) {
WATCHDOG_RESET ();
__asm__("eieio");
}
}
int smc1_getc(void)
{
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
/* Wait for character to show up.
*/
buf = (unsigned char *)rbdf->cbd_bufaddr;
while (rbdf->cbd_sc & BD_SC_EMPTY)
WATCHDOG_RESET ();
c = *buf;
rbdf->cbd_sc |= BD_SC_EMPTY;
return(c);
}
int smc1_tstc(void)
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
}
/* search for keyboard and register it if found */
int drv_keyboard_init(void)
{
int error = 0;
device_t kbd_dev;
if (0) {
/* register the keyboard */
memset (&kbd_dev, 0, sizeof(device_t));
strcpy(kbd_dev.name, "kbd");
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbd_dev.putc = NULL;
kbd_dev.puts = NULL;
kbd_dev.getc = smc1_getc;
kbd_dev.tstc = smc1_tstc;
error = device_register (&kbd_dev);
} else {
lcd_is_enabled = 0;
lcd_disable();
}
return error;
}
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "mpc8xx.h"
#include <linux/mtd/doc2000.h>
extern int kbd_init(void);
extern int drv_kbd_init(void);
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x1FF7FC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
const uint static_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
0xFFFFFC04, 0xFFFFFC05, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity: