Commit 684a501e authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu

sh: boards: Change clock definition of SCIF and TMU

This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_TMU_CLK_FREQ for boards.
Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
parent f8b7d9ea
......@@ -123,6 +123,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -155,6 +155,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -158,6 +158,8 @@
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -179,6 +179,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 41666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -98,6 +98,8 @@
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -67,6 +67,8 @@
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -85,6 +85,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -111,6 +111,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -82,6 +82,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -164,6 +164,8 @@
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -77,6 +77,8 @@
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
......
......@@ -102,6 +102,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -85,6 +85,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
......
......@@ -65,6 +65,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 36000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
......
......@@ -64,6 +64,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 66125000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
......
......@@ -132,6 +132,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __SH7752EVB_H */
......@@ -140,6 +140,8 @@
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __SH7757LCR_H */
......@@ -98,6 +98,8 @@
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
......
......@@ -172,6 +172,8 @@
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
......@@ -103,6 +103,8 @@
#else
#define CONFIG_SYS_CLK_FREQ 33333333
#endif /* CONFIG_T_SH7706LSR */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
......
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