Commit 690e4258 authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by York Sun

powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI

Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.

Also add their details in README.
Signed-off-by: 's avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: 's avatarYork Sun <yorksun@freescale.com>
parent 3fdc827c
......@@ -419,8 +419,8 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.pbl: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
$(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \
-R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \
-d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
......
......@@ -472,6 +472,15 @@ The following options need to be configured:
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details
CONFIG_SYS_FSL_PBL_RCW
It adds PBI(pre-boot instructions) commands in u-boot build image.
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
......
......@@ -16,8 +16,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
......
......@@ -18,8 +18,9 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
......
......@@ -32,8 +32,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
#endif
/* High Level Configuration Options */
......
......@@ -45,8 +45,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
......
......@@ -21,8 +21,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
......
......@@ -15,15 +15,19 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#if defined(CONFIG_P3041DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
#define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
#elif defined(CONFIG_P4080DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
#define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
#elif defined(CONFIG_P5040DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#define CONFIG_SYS_FSL_PBL_RCW \
$(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
......
......@@ -24,8 +24,8 @@
#define CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */
#define CONFIG_BOOKE
......
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