Commit 6e60ea84 authored by Ye Li's avatar Ye Li

MLK-18230 imx8qxp: Set back usdhc clock parent to PLL0 for B0

8QXP B0 chip already fix the DPLL unstable issue, so we set back the
usdhc clock parent to PLL0 (DPLL) for B0 chip. A0 chip will remain use the
PLL1 (AVPLL).
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
Reviewed-by: 's avatarPeng Fan <peng.fan@nxp.com>
parent 850d6d05
......@@ -299,14 +299,14 @@ void init_clk_usdhc(u32 index)
* USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD
* SDR104 work at 200MHz.
*/
#ifdef CONFIG_IMX8QXP
err = sc_pm_set_clock_parent(ipc, usdhcs[index], 2, SC_PM_PARENT_PLL1);
if (err != SC_ERR_NONE)
printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err);
if (is_imx8qxp() && is_soc_rev(CHIP_REV_A)) {
err = sc_pm_set_clock_parent(ipc, usdhcs[index], 2, SC_PM_PARENT_PLL1);
if (err != SC_ERR_NONE)
printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err);
if (index == 1)
actual = 200000000;
#endif
if (index == 1)
actual = 200000000;
}
err = sc_pm_set_clock_rate(ipc, usdhcs[index], 2, &actual);
if (err != SC_ERR_NONE) {
......@@ -315,7 +315,7 @@ void init_clk_usdhc(u32 index)
}
if (actual != 400000000)
printf("Actual rate for SDHC_%d is %d\n", index, actual);
debug("Actual rate for SDHC_%d is %d\n", index, actual);
err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, true, false);
if (err != SC_ERR_NONE) {
......
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