Commit 7288c2c2 authored by York Sun's avatar York Sun

armv8/ls2085aqds: Add support of LS2085AQDS platform

The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@freescale.com>
parent 9cc2c471
......@@ -711,6 +711,16 @@ config TARGET_LS2085A_SIMU
select ARM64
select ARMV8_MULTIENTRY
config TARGET_LS2085AQDS
bool "Support ls2085aqds"
select ARM64
select ARMV8_MULTIENTRY
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
......@@ -865,6 +875,7 @@ source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/mx23evk/Kconfig"
......
......@@ -11,28 +11,82 @@ for example LS2085A.
Flash Layout
============
A typical layout of various images (including Linux and other firmware images)
is shown below considering a 32MB NOR flash device:
(1) A typical layout of various images (including Linux and other firmware images)
is shown below considering a 32MB NOR flash device present on most
pre-silicon platforms (simulator and emulator):
-------------------------
| linux |
| FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
| Debug Server |
| Debug Server FW |
------------------------- ----> 0x00C0_0000
| AIOP SW |
| AIOP FW |
------------------------- ----> 0x0070_0000
| MC FW |
------------------------- ----> 0x006C_0000
| MC Data Path Layout |
| MC DPL Blob |
------------------------- ----> 0x0020_0000
| BootLoader |
| BootLoader + Env|
------------------------- ----> 0x0000_1000
| PBI |
------------------------- ----> 0x0000_0080
| RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
(2) A typical layout of various images (including Linux and other firmware images)
is shown below considering a 128MB NOR flash device present on QDS
boards:
----------------------------------------- ----> 0x5_8800_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
| PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
| MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
| MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
| BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
| RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
| PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
| MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
| MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
| BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
| RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS board
Environment Variables
=====================
......
if TARGET_LS2085AQDS
config SYS_BOARD
default "ls2085aqds"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-lsch3"
config SYS_CONFIG_NAME
default "ls2085aqds"
endif
LS2085A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
S: Maintained
F: board/freescale/ls2085aqds/
F: board/freescale/ls2085a/ls2085aqds.c
F: include/configs/ls2085aqds.h
F: configs/ls2085aqds_defconfig
#
# Copyright 2015 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls2085aqds.o
obj-y += ddr.o
Overview
--------
The LS2085A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2085A
Layerscape Architecture processor. The LS2085AQDS provides validation and
SW development platform for the Freescale LS2085A processor series, with
a complete debugging environment.
LS2085A SoC Overview
------------------
The LS2085A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
The LS2085A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
the AIOP
- Data path acceleration architecture (DPAA2) incorporating acceleration for
the following functions:
- Packet parsing, classification, and distribution (WRIOP)
- Queue and Hardware buffer management for scheduling, packet sequencing, and
congestion management, buffer allocation and de-allocation (QBMan)
- Cryptography acceleration (SEC) at up to 10 Gbps
- RegEx pattern matching acceleration (PME) at up to 10 Gbps
- Decompression/compression acceleration (DCE) at up to 20 Gbps
- Accelerated I/O processing (AIOP) at up to 20 Gbps
- QDMA engine
- 16 SerDes lanes at up to 10.3125 GHz
- Ethernet interfaces
- Up to eight 10 Gbps Ethernet MACs
- Up to eight 1 / 2.5 Gbps Ethernet MACs
- High-speed peripheral interfaces
- Four PCIe 3.0 controllers, one supporting SR-IOV
- Additional peripheral interfaces
- Two serial ATA (SATA 3.0) controllers
- Two high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Serial peripheral interface (SPI) controller
- Quad Serial Peripheral Interface (QSPI) Controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
LS2085AQDS board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- XAUI
- XFI
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
- One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
and two DIMM connectors. Support is up to 1600MT/s.
-IFC/Local Bus
- IFC rev. 2.0 implementation supporting Little Endian connection scheme.
- One in-socket 128 MB NOR flash 16-bit data bus
- One 512 MB NAND flash with ECC support
- IFC Test Port
- PromJet Port
- FPGA connection
- USB 3.0
- Two high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- Second USB 3.0 port configured as OTG with micro-AB connector
- SDHC: PCIe x1 Right Angle connector for supporting following cards
- 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
- 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
- 4-bit eMMC Card Rev 4.4 (1.8V only)
- 8-bit eMMC Card Rev 4.5 (1.8V only)
- SD Card Rev 2.0 and Rev 3.0
- DSPI: 3 high-speed flash Memory for storage
- 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- 8 MB high-speed flash Memory (up to 104 MHz)
- 512 MB low-speed flash Memory (up to 40 MHz)
- QSPI: via NAND/QSPI Card
- 4 I2C controllers
- Two SATA onboard connectors
- UART
- Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
- Two DB9 D-Type connectors supporting one Serial port each
- ARM JTAG support
Memory map from core's view
----------------------------
0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
Other addresses are either reserved, or not used directly by u-boot.
This list should be updated when more addresses are used.
IFC region map from core's view
-------------------------------
During boot i.e. IFC Region #1:-
0x30000000 - 0x37ffffff : 128MB : NOR flash
0x38000000 - 0x3BFFFFFF : 64MB : Promjet
0x3C000000 - 0x40000000 : 64MB : FPGA etc
After relocate to DDR i.e. IFC Region #2:-
0x5_1000_0000..0x5_1fff_ffff Memory Hole
0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
Booting Options
---------------
a) Promjet Boot
b) NOR boot
c) NAND boot
d) SD boot
e) QSPI boot
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
if (pdimm[slot].n_ranks)
break;
}
if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
return;
/*
* we use identical timing for all slots. If needed, change the code
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
*/
if (popts->registered_dimm_en)
pbsp = rdimms[ctrl_num];
else
pbsp = udimms[ctrl_num];
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm[slot].n_ranks &&
(pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found for data rate %lu MT/s\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
popts->otf_burst_chop_en = 0;
popts->burst_length = DDR_BL8;
popts->bstopre = 0; /* enable auto precharge */
/*
* Layout optimization results byte mapping
* Byte 0 -> Byte ECC
* Byte 1 -> Byte 3
* Byte 2 -> Byte 2
* Byte 3 -> Byte 1
* Byte ECC -> Byte 0
*/
dq_mapping_0 = pdimm[slot].dq_mapping[0];
dq_mapping_2 = pdimm[slot].dq_mapping[2];
dq_mapping_3 = pdimm[slot].dq_mapping[3];
pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
pdimm[slot].dq_mapping[6] = dq_mapping_2;
pdimm[slot].dq_mapping[7] = dq_mapping_3;
pdimm[slot].dq_mapping[8] = dq_mapping_0;
pdimm[slot].dq_mapping[9] = 0;
pdimm[slot].dq_mapping[10] = 0;
pdimm[slot].dq_mapping[11] = 0;
pdimm[slot].dq_mapping[12] = 0;
pdimm[slot].dq_mapping[13] = 0;
pdimm[slot].dq_mapping[14] = 0;
pdimm[slot].dq_mapping[15] = 0;
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0x0; /* 32 clocks */
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
if (ddr_freq < 2350) {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
DDR_CDR2_VREF_RANGE_2;
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
DDR_CDR2_VREF_RANGE_2;
}
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
return dram_size;
}
void dram_init_banksize(void)
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
#endif
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
/* initialize DP-DDR here */
puts("DP-DDR: ");
/*
* DDR controller use 0 as the base address for binding.
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
*/
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
if (dp_ddr_size) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
gd->bd->bi_dram[2].size = dp_ddr_size;
} else {
puts("Not detected");
}
#endif
}
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR_H__
#define __DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{}
};
/* DP-DDR DIMM */
static const struct board_specific_parameters udimm2[] = {
/*
* memory controller 2
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
{2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{}
};
/* DP-DDR DIMM */
static const struct board_specific_parameters rdimm2[] = {
/*
* memory controller 2
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
udimm0,
udimm2,
};
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
rdimm0,
rdimm2,
};
#endif
/*
* Copyright 2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
#include <asm/arch-fsl-lsch3/soc.h>
#include "../common/qixis.h"
#include "ls2085aqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
if (gd->flags & GD_FLG_RELOC)
addr = QIXIS_BASE_PHYS;
else
addr = QIXIS_BASE_PHYS_EARLY;
/*
* IFC address under 256MB is mapped to 0x30000000, any address above
* is mapped to 0x5_10000000 up to 4GB.
*/
addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
return addr;
}
int checkboard(void)
{
char buf[64];
u8 sw;
static const char *const freq[] = {"100", "125", "156.25",
"100 separate SSCG"};
int clock;
sw = QIXIS_READ(arch);
printf("Board: %s, ", CONFIG_IDENT_STRING);
printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
* values that the SERDES expects (or vice versa). For now, however,
* we just display both values and hope the user notices when they
* don't match.
*/
puts("SERDES1 Reference : ");
sw = QIXIS_READ(brdcfg[2]);
clock = (sw >> 6) & 3;
printf("Clock1 = %sMHz ", freq[clock]);
clock = (sw >> 4) & 3;
printf("Clock2 = %sMHz", freq[clock]);
puts("\nSERDES2 Reference : ");
clock = (sw >> 2) & 3;
printf("Clock1 = %sMHz ", freq[clock]);
clock = (sw >> 0) & 3;
printf("Clock2 = %sMHz\n", freq[clock]);
return 0;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
int board_init(void)
{
init_final_memctl_regs();
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);