Commit 73cc2f50 authored by Aneesh Bansal's avatar Aneesh Bansal Committed by York Sun

powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: default avatarSaksham Jain <saksham@freescale.com>
Signed-off-by: default avatarRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: default avatarAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 467a40df
......@@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
F: configs/P5040DS_NAND_SECURE_BOOT_defconfig
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SPI_FLASH=y
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