Commit 7594571c authored by Han Xu's avatar Han Xu Committed by Jason Liu

MLK-16034-03: support NAND on i.MX8QXP ARM2 board

NAND module is pin conflict with SD/eMMC on i.MX8QXP ARM2 board,
add new config to disable SD/eMMC when booting from NAND.
Signed-off-by: default avatarHan Xu <han.xu@nxp.com>
parent 474c4270
......@@ -168,6 +168,45 @@ void init_clk_fspi(int index)
return;
}
void init_clk_gpmi_nand(void)
{
sc_err_t sciErr = 0;
sc_pm_clock_rate_t rate;
sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle;
/* Set NAND BCH clock root to 50 MHz */
rate = 50000000;
sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_NAND, SC_PM_CLK_PER, &rate);
if (sciErr != SC_ERR_NONE) {
puts("NAND BCH set rate failed\n");
return;
}
/* Enable NAND BCH clock root */
sciErr = sc_pm_clock_enable(ipcHndl, SC_R_NAND, SC_PM_CLK_PER, true, false);
if (sciErr != SC_ERR_NONE) {
puts("NAND BCH enable clock failed\n");
return;
}
/* Set NAND GPMI clock root to 50 MHz */
rate = 50000000;
sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_NAND, SC_PM_CLK_MST_BUS, &rate);
if (sciErr != SC_ERR_NONE) {
puts("NAND GPMI set rate failed\n");
return;
}
/* Enable NAND GPMI clock root */
sciErr = sc_pm_clock_enable(ipcHndl, SC_R_NAND, SC_PM_CLK_MST_BUS, true, false);
if (sciErr != SC_ERR_NONE) {
puts("NAND GPMI enable clock failed\n");
return;
}
return;
}
void enable_usboh3_clk(unsigned char enable)
{
return;
......
......@@ -32,5 +32,6 @@ void enable_usboh3_clk(unsigned char enable);
int set_clk_qspi(void);
u32 imx_get_fecclk(void);
void init_clk_usdhc(u32 index);
void init_clk_gpmi_nand(void);
#endif /* __ASM_ARCH_CLOCK_H__ */
......@@ -26,6 +26,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/video.h>
#include <asm/imx-common/dma.h>
#include <asm/arch/video_common.h>
#include <power-domain.h>
......@@ -34,6 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
| (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
......@@ -136,6 +140,11 @@ int board_mmc_init(bd_t *bis)
int i, ret;
struct power_domain pd;
#ifdef CONFIG_NAND_BOOT
return 0;
#endif
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
......@@ -333,6 +342,61 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
#ifdef CONFIG_NAND_BOOT
static iomux_cfg_t gpmi_nand_pads[] = {
SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
/* i.MX8QXP NAND use nand_re_dqs_pins */
SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
SC_P_USDHC1_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
};
static void setup_iomux_gpmi_nand(void)
{
imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
}
static void imx8qm_gpmi_nand_initialize(void)
{
int ret;
struct power_domain pd;
if (!power_domain_lookup_name("conn_dma4_ch0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("conn_dma4_ch0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("conn_nand", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("conn_nand Power up failed! (error = %d)\n", ret);
}
init_clk_gpmi_nand();
setup_iomux_gpmi_nand();
mxs_dma_init();
}
#endif
static int setup_fec(int ind)
{
/* Reset ENET PHY */
......@@ -450,6 +514,10 @@ int board_init(void)
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
#ifdef CONFIG_NAND_BOOT
imx8qm_gpmi_nand_initialize();
#endif
#ifdef CONFIG_USB_EHCI_MX6
setup_otg();
#endif
......
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_CMD_GPIO=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_BOOTDELAY=3
CONFIG_IMX_BOOTAUX=y
CONFIG_CMD_FAT=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_BOOT=y
CONFIG_FSL_FSPI=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_4BYTES_ADDR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_DM_ETH=y
# CONFIG_EFI_LOADER is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_VIDEO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
......@@ -168,6 +168,12 @@
"booti; " \
"fi;\0"
#ifdef CONFIG_NAND_BOOT
#define CONFIG_BOOTCOMMAND \
"nand read ${loadaddr} 0x4000000 0x800000;"\
"nand read ${fdtaddr} 0x5000000 0x100000;"\
"booti ${loadaddr} - ${fdtaddr}"
#else
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
......@@ -179,6 +185,7 @@
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdtaddr}; fi"
#endif
/* Link Definitions */
#define CONFIG_LOADADDR 0x80280000
......@@ -190,11 +197,17 @@
/* Default environment is in SD */
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (64 << 20)
#else
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#endif
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
*/
......@@ -252,6 +265,23 @@
#define CONFIG_SYS_FSL_FSPI_AHB
#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_NAND_MXS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
#endif
/* USB OTG controller configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_HOST_ETHER
......
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