Commit 765b0bdb authored by Priyanka Jain's avatar Priyanka Jain Committed by Andy Fleming

board/bsc9131rdb: Add DSP side tlb and laws

BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 087cf44f
......@@ -422,6 +422,13 @@ The following options need to be configured:
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
This value denotes start offset of M2 memory
which is directly connected to the DSP core.
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
......
......@@ -494,6 +494,8 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......
......@@ -82,11 +82,16 @@ enum law_trgt_if {
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
#if defined(CONFIG_BSC9131)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_DSP_CCSR = 0x09,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_RIO_2 = 0x0d,
......
......@@ -26,6 +26,10 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_DSP_CCSR),
SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
LAW_TRGT_IF_OCN_DSP),
};
int num_law_entries = ARRAY_SIZE(law_table);
......@@ -52,6 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* CCSRBAR (DSP) */
SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
......
......@@ -153,16 +153,21 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
/* DSP CCSRBAR */
#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
/*
* Memory map
*
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
* 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
* 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
*
......
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