Commit 7a4f511b authored by David Brownell's avatar David Brownell Committed by Wolfgang Denk

davinci: display correct clock info

Move the clock-rate dumping code into the cpu/.../davinci area
where it should have been, enabled by CONFIG_DISPLAY_CPUINFO,
updating the format and showing the DSP clock (where relevant).

Switch boards to use the cpuinfo() hook for this stuff.

Remove a few now-obsolete PLL #defines.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
parent daea9288
......@@ -28,6 +28,7 @@
#include <net.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
......@@ -38,18 +39,6 @@ int dram_init(void)
return(0);
}
static int dv_get_pllm_output(uint32_t pllm)
{
return (pllm + 1) * (CONFIG_SYS_HZ_CLOCK / 1000000);
}
void dv_display_clk_infos(void)
{
printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2);
printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) /
((REG(PLL2_DIV2) & 0x1f) + 1) / 2);
}
#ifdef CONFIG_DRIVER_TI_EMAC
/* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
......
......@@ -24,7 +24,6 @@
extern int eth_hw_init(void);
void dv_display_clk_infos(void);
int dvevm_read_mac_address(uint8_t *buf);
void dv_configure_mac_address(uint8_t *rom_enetaddr);
......
......@@ -69,8 +69,6 @@ int misc_init_r(void)
uint8_t video_mode;
uint8_t eeprom_enetaddr[6];
dv_display_clk_infos();
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
dv_configure_mac_address(eeprom_enetaddr);
......
......@@ -104,8 +104,6 @@ int misc_init_r(void)
0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
};
dv_display_clk_infos();
/* Set serial number from UID chip */
if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
......
......@@ -131,8 +131,6 @@ int misc_init_r(void)
/* EMIF-A CS3 configuration for FPGA. */
REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
dv_display_clk_infos();
/* Configure I2C switch (PCA9543) to enable channel 0. */
i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
......
......@@ -66,8 +66,6 @@ int misc_init_r(void)
{
uint8_t eeprom_enetaddr[6];
dv_display_clk_infos();
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
dv_configure_mac_address(eeprom_enetaddr);
......
......@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS-y += timer.o psc.o
COBJS-y += cpu.o timer.o psc.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o
......
/*
* Copyright (C) 2004 Texas Instruments.
* Copyright (C) 2009 David Brownell
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/arch/hardware.h>
/* offsets from PLL controller base */
#define PLLC_PLLCTL 0x100
#define PLLC_PLLM 0x110
#define PLLC_PREDIV 0x114
#define PLLC_PLLDIV1 0x118
#define PLLC_PLLDIV2 0x11c
#define PLLC_PLLDIV3 0x120
#define PLLC_POSTDIV 0x128
#define PLLC_BPDIV 0x12c
#define PLLC_PLLDIV4 0x160
#define PLLC_PLLDIV5 0x164
#define PLLC_PLLDIV6 0x168
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
#define BIT(x) (1 << (x))
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_SOC_DM644X
#define ARM_PLLDIV PLLC_PLLDIV2
#define DSP_PLLDIV PLLC_PLLDIV1
#define DDR_PLLDIV PLLC_PLLDIV2
#endif
#ifdef CONFIG_SOC_DM6447
#define ARM_PLLDIV PLLC_PLLDIV2
#define DSP_PLLDIV PLLC_PLLDIV1
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
static unsigned pll_div(volatile void *pllbase, unsigned offset)
{
u32 div;
div = REG(pllbase + offset);
return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
}
static inline unsigned pll_prediv(volatile void *pllbase)
{
#ifdef CONFIG_SOC_DM355
/* this register read seems to fail on pll0 */
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
return 8;
else
return pll_div(pllbase, PLLC_PREDIV);
#endif
return 1;
}
static inline unsigned pll_postdiv(volatile void *pllbase)
{
#ifdef CONFIG_SOC_DM355
return pll_div(pllbase, PLLC_POSTDIV);
#elif defined(CONFIG_SOC_DM6446)
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
return pll_div(pllbase, PLLC_POSTDIV);
#endif
return 1;
}
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{
volatile void *pllbase = (volatile void *) pll_addr;
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
/* the PLL might be bypassed */
if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
base /= pll_prediv(pllbase);
base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
base /= pll_postdiv(pllbase);
}
return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
}
int print_cpuinfo(void)
{
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
printf("Cores: ARM %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
#ifdef DSP_PLLDIV
printf(", DSP %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
#endif
printf("\nDDR: %d MHz\n",
/* DDR PHY uses an x2 input clock */
pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
/ 2);
return 0;
}
#endif
......@@ -175,11 +175,6 @@ void davinci_errata_workarounds(void);
#define PSC_SILVER_BULLET (0x01c41a20)
/* Some PLL defines */
#define PLL1_PLLM (0x01c40910)
#define PLL2_PLLM (0x01c40d10)
#define PLL2_DIV2 (0x01c40d1c)
/* Miscellania... */
#define VBPR (0x20000020)
......
......@@ -52,6 +52,7 @@
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/*===================*/
......
......@@ -27,6 +27,7 @@
#define SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/*===================*/
......
......@@ -28,8 +28,8 @@
#define SFFSDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* This is to prevent U-Boot from
* powering ON the DSP. */
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
......
......@@ -52,6 +52,7 @@
#define SONATA_BOARD
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/*===================*/
......
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