Commit 7ac9d47a authored by Matthias Fuchs's avatar Matthias Fuchs Committed by Tom Rini

ppc4xx: remove DU440 board

Signed-off-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
parent bc114076
......@@ -125,9 +125,6 @@ config TARGET_CPCI405AB
config TARGET_CPCI405DT
bool "Support CPCI405DT"
config TARGET_DU440
bool "Support DU440"
config TARGET_HH405
bool "Support HH405"
......@@ -238,7 +235,6 @@ source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/du440/Kconfig"
source "board/esd/hh405/Kconfig"
source "board/esd/hub405/Kconfig"
source "board/esd/ocrtc/Kconfig"
......
if TARGET_DU440
config SYS_BOARD
default "du440"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "DU440"
endif
DU440 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/du440/
F: include/configs/DU440.h
F: configs/DU440_defconfig
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = du440.o
extra-y += init.o
#
# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
This diff is collapsed.
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDR0_USB0 0x0320 /* USB Control Register */
#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
#define CPLD_VERSION_MASK 0x0f
#define PWR_INT_FLAG 0x80
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
/* TLB-entry for PCI IO */
tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
/* TLB-entry for NAND */
tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
/* TLB-entry for Internal Registers & OCM */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
/* TLB-entry PCI registers */
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
tlbtab_end
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_DU440=y
......@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
CPCIISER4 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
......
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment