Commit 7b973f17 authored by Ye Li's avatar Ye Li

MLK-14391-3 mx6sxarm2: Convert to enable OF_CONTROL and DM drivers

Update mx6sx 14x14/17x17/19x19 lpddr2/ddr3 arm2 board codes and build
configurations to enable OF_CONTROL and DM drivers.

1. Update GPIO codes for adding gpio request
2. Enable USB DM driver
3. Update PMIC code for using DM PMIC
4. Add spinor/qspi/nand/eimnor boot support.
5. Add defconfig for using plugin.
6. Enable Ethernet DM driver
7. Update for using QSPI DM driver
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent 9496b976
......@@ -11,4 +11,10 @@ config SYS_CONFIG_NAME
config LPDDR2
bool "Select for the board using LPDDR2 not default DDR3"
config NOR
bool "Support for NOR flash"
help
The i.MX SoC supports having a NOR flash connected to the WEIM.
Need to set this for NOR_BOOT.
endif
......@@ -21,9 +21,9 @@ IMAGE_VERSION 2
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
......
......@@ -21,9 +21,9 @@ IMAGE_VERSION 2
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
......
......@@ -21,9 +21,9 @@ IMAGE_VERSION 2
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
......
......@@ -28,7 +28,8 @@
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
#include <usb/ehci-ci.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -76,9 +77,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PMIC 0
#ifdef CONFIG_SYS_I2C_MXC
#ifdef CONFIG_SYS_I2C
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
......@@ -107,8 +106,11 @@ struct i2c_pads_info i2c_pad_info2 = {
.gp = IMX_GPIO_NR(1, 3),
},
};
#endif
#ifdef CONFIG_POWER
static struct pmic *pfuze;
#define I2C_PMIC 0
int power_init_board(void)
{
unsigned int reg;
......@@ -199,6 +201,64 @@ void ldo_mode_set(int ldo_bypass)
}
#endif
#elif defined(CONFIG_DM_PMIC_PFUZE100)
int power_init_board(void)
{
struct udevice *dev;
int ret;
dev = pfuze_common_init();
if (!dev)
return -ENODEV;
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
return 0;
}
#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
struct udevice *dev;
int ret;
int is_400M;
u32 vddarm;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode , boot on 800Mhz */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
/* increase VDDSOC to 1.3V */
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
is_400M = set_anatop_bypass(1);
if (is_400M)
vddarm = PFUZE100_SW1ABC_SETP(10750);
else
vddarm = PFUZE100_SW1ABC_SETP(11750);
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
/* decrease VDDSOC to 1.175V */
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
#endif
#endif
int dram_init(void)
......@@ -275,11 +335,6 @@ static iomux_v3_cfg_t const fec1_pads[] = {
static void setup_iomux_fec1(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(4, 22) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(4, 22), 1);
}
#endif
......@@ -289,7 +344,7 @@ static void setup_iomux_uart(void)
}
#ifdef CONFIG_FSL_QSPI
#ifndef CONFIG_DM_SPI
#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
......@@ -311,11 +366,14 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
#endif
int board_qspi_init(void)
{
#ifndef CONFIG_DM_SPI
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
#endif
/* Set the clock */
enable_qspi_clk(1);
......@@ -335,7 +393,7 @@ static struct fsl_esdhc_cfg usdhc_cfg[3] = {
int board_mmc_get_env_dev(int dev_no)
{
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
dev_no -= 2;
#else
dev_no--;
......@@ -346,7 +404,7 @@ int board_mmc_get_env_dev(int dev_no)
int mmc_map_to_kernel_blk(int dev_no)
{
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
return dev_no + 2;
#else
return dev_no + 1;
......@@ -373,7 +431,7 @@ int board_mmc_getcd(struct mmc *mmc)
return ret;
}
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
int board_mmc_init(bd_t *bis)
{
int i;
......@@ -389,6 +447,7 @@ int board_mmc_init(bd_t *bis)
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
......@@ -432,6 +491,7 @@ int board_mmc_init(bd_t *bis)
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
......@@ -455,7 +515,7 @@ int board_mmc_init(bd_t *bis)
#endif
#endif
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
......@@ -467,6 +527,7 @@ void setup_spinor(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi4_pads,
ARRAY_SIZE(ecspi4_pads));
gpio_request(IMX_GPIO_NR(6, 10), "ecspi cs");
gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
}
......@@ -476,7 +537,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
}
#endif
#ifdef CONFIG_SYS_USE_EIMNOR
#ifdef CONFIG_MTD_NOR_FLASH
iomux_v3_cfg_t eimnor_pads[] = {
MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
......@@ -531,7 +592,7 @@ static void setup_eimnor(void)
}
#endif
#ifdef CONFIG_SYS_USE_NAND
#ifdef CONFIG_NAND_MXS
iomux_v3_cfg_t gpmi_pads[] = {
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
......@@ -581,6 +642,9 @@ int board_eth_init(bd_t *bis)
return 0;
}
#define MAX7322_I2C_ADDR 0x68
#define MAX7322_I2C_BUS 1
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
......@@ -595,18 +659,43 @@ static int setup_fec(void)
if (ret)
return ret;
#ifdef CONFIG_FEC_ENABLE_MAX7322
/* release max7322 from reset */
gpio_direction_output(IMX_GPIO_NR(4, 22) , 1);
/* Reset AR8031 PHY */
gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset");
gpio_direction_output(IMX_GPIO_NR(4, 22) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(4, 22), 1);
#ifdef CONFIG_DM_I2C
struct udevice *bus, *dev;
ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus);
if (ret) {
printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret);
return ret;
}
ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev);
if (ret) {
printf("MAX7322 Not found, ret = %d\n", ret);
return ret;
}
/* Write 0x1 to enable O0 output, this device has no addr */
/* hence addr length is 0 */
value = 0x1;
ret = dm_i2c_write(dev, 0, &value, 1);
if (ret) {
printf("MAX7322 write failed, ret = %d\n", ret);
return ret;
}
#else
/* This is needed to drive the pads to 1.8V instead of 1.5V */
i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
i2c_set_bus_num(MAX7322_I2C_BUS);
if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
if (!i2c_probe(MAX7322_I2C_ADDR)) {
/* Write 0x1 to enable O0 output, this device has no addr */
/* hence addr length is 0 */
value = 0x1;
if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1))
printf("MAX7322 write failed\n");
} else {
printf("MAX7322 Not found\n");
......@@ -685,7 +774,7 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
#ifdef CONFIG_SYS_I2C
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#endif
......@@ -694,15 +783,15 @@ int board_init(void)
setup_fec();
#endif
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
setup_spinor();
#endif
#ifdef CONFIG_SYS_USE_EIMNOR
#ifdef CONFIG_MTD_NOR_FLASH
setup_eimnor();
#endif
#ifdef CONFIG_SYS_USE_NAND
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
......
......@@ -12,4 +12,9 @@ config SYS_CONFIG_NAME
config LPDDR2
bool "Select for the board using LPDDR2 not default DDR3"
config NOR
bool "Support for NOR flash"
help
The i.MX SoC supports having a NOR flash connected to the WEIM.
Need to set this for NOR_BOOT.
endif
......@@ -21,9 +21,9 @@ IMAGE_VERSION 2
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
......
......@@ -21,9 +21,9 @@ IMAGE_VERSION 2
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
#ifdef CONFIG_QSPI_BOOT
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM nor
#else
BOOT_FROM sd
......
......@@ -28,8 +28,9 @@
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
#include <usb/ehci-ci.h>
#include <asm/imx-common/video.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -77,9 +78,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PMIC 0
#ifdef CONFIG_SYS_I2C_MXC
#ifdef CONFIG_SYS_I2C
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
......@@ -108,8 +107,11 @@ struct i2c_pads_info i2c_pad_info2 = {
.gp = IMX_GPIO_NR(1, 3),
},
};
#endif
#ifdef CONFIG_POWER
static struct pmic *pfuze;
#define I2C_PMIC 0
int power_init_board(void)
{
unsigned int reg;
......@@ -200,6 +202,64 @@ void ldo_mode_set(int ldo_bypass)
}
#endif
#elif defined(CONFIG_DM_PMIC_PFUZE100)
int power_init_board(void)
{
struct udevice *dev;
int ret;
dev = pfuze_common_init();
if (!dev)
return -ENODEV;
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
return 0;
}
#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
struct udevice *dev;
int ret;
int is_400M;
u32 vddarm;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode , boot on 800Mhz */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
/* increase VDDSOC to 1.3V */
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
is_400M = set_anatop_bypass(1);
if (is_400M)
vddarm = PFUZE100_SW1ABC_SETP(10750);
else
vddarm = PFUZE100_SW1ABC_SETP(11750);
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
/* decrease VDDSOC to 1.175V */
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
#endif
#endif
int dram_init(void)
......@@ -277,29 +337,33 @@ struct lcd_panel_info_t {
void do_enable_lvds(struct display_info_t const *dev)
{
enable_lcdif_clock(dev->bus);
enable_lcdif_clock(dev->bus, 1);
enable_lvds_bridge(dev->bus);
imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
ARRAY_SIZE(lvds_ctrl_pads));
/* Enable CABC */
gpio_request(IMX_GPIO_NR(2, 16), "cabc enable");
gpio_direction_output(IMX_GPIO_NR(2, 16) , 1);
/* Set Brightness to high */
gpio_request(IMX_GPIO_NR(1, 12), "backlight");
gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
}
void do_enable_parallel_lcd(struct display_info_t const *dev)
{
enable_lcdif_clock(dev->bus);
enable_lcdif_clock(dev->bus, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Power up the LCD */
gpio_request(IMX_GPIO_NR(3, 27), "lcd pwr");
gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
/* Set Brightness to high */
gpio_request(IMX_GPIO_NR(1, 12), "backlight");
gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
}
......@@ -379,7 +443,7 @@ static void setup_iomux_uart(void)
}
#ifdef CONFIG_FSL_QSPI
#ifndef CONFIG_DM_SPI
#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
......@@ -401,11 +465,14 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
#endif
int board_qspi_init(void)
{
#ifndef CONFIG_DM_SPI
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
#endif
/* Set the clock */
enable_qspi_clk(1);
......@@ -437,7 +504,7 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
......@@ -449,6 +516,7 @@ void setup_spinor(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi4_pads,
ARRAY_SIZE(ecspi4_pads));
gpio_request(IMX_GPIO_NR(6, 10), "ecspi cs");
gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
}
......@@ -458,7 +526,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
}
#endif
#ifdef CONFIG_SYS_USE_EIMNOR
#ifdef CONFIG_MTD_NOR_FLASH
iomux_v3_cfg_t eimnor_pads[] = {
MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
......@@ -530,8 +598,7 @@ static void setup_eimnor(void)
}
#endif
#ifdef CONFIG_SYS_USE_NAND
#ifdef CONFIG_NAND_MXS
iomux_v3_cfg_t gpmi_pads[] = {
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
......@@ -567,6 +634,10 @@ static void setup_gpmi_nand(void)
#endif
#ifdef CONFIG_FEC_MXC
#define MAX7322_I2C_ADDR 0x68
#define MAX7322_I2C_BUS 1
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
......@@ -582,19 +653,42 @@ static int setup_fec(void)
return ret;
/* Reset AR8031 PHY */
gpio_request(IMX_GPIO_NR(6, 18), "ar8031 reset");
gpio_direction_output(IMX_GPIO_NR(6, 18) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(6, 18), 1);
#ifdef CONFIG_FEC_ENABLE_MAX7322
#ifdef CONFIG_DM_I2C
struct udevice *bus, *dev;
ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus);
if (ret) {
printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret);
return ret;
}
ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev);
if (ret) {
printf("MAX7322 Not found, ret = %d\n", ret);
return ret;
}
/* Write 0x1 to enable O0 output, this device has no addr */
/* hence addr length is 0 */
value = 0x1;
ret = dm_i2c_write(dev, 0, &value, 1);
if (ret) {
printf("MAX7322 write failed, ret = %d\n", ret);
return ret;
}
#else
/* This is needed to drive the pads to 1.8V instead of 1.5V */
i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
i2c_set_bus_num(MAX7322_I2C_BUS);
if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
if (!i2c_probe(MAX7322_I2C_ADDR)) {
/* Write 0x1 to enable O0 output, this device has no addr */
/* hence addr length is 0 */
value = 0x1;
if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1))
printf("MAX7322 write failed\n");
} else {
printf("MAX7322 Not found\n");
......@@ -609,7 +703,6 @@ int board_eth_init(bd_t *bis)
int ret;
setup_iomux_fec1();
setup_fec();
ret = fecmxc_initialize_multi(bis, 0,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
......@@ -691,20 +784,24 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
#ifdef CONFIG_SYS_I2C
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#endif
#ifdef CONFIG_SYS_USE_SPINOR
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#ifdef CONFIG_MXC_SPI
setup_spinor();
#endif
#ifdef CONFIG_SYS_USE_EIMNOR
#ifdef CONFIG_MTD_NOR_FLASH
setup_eimnor();
#endif
#ifdef CONFIG_SYS_USE_NAND
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
......
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SX_14X14_ARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,LPDDR2"
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-arm2"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg"
CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-arm2.dtb"
CONFIG_LPDDR2=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_ETH=y
CONFIG_DM_USB=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_IMX_BOOTAUX=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SX_14X14_ARM2=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg,LPDDR2,SYS_BOOT_NAND"
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-arm2"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg"
CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-arm2.dtb"
CONFIG_NAND_BOOT=y
CONFIG_LPDDR2=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set