Commit 7cad2e38 authored by Ruchika Gupta's avatar Ruchika Gupta Committed by York Sun

powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot

By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them once the control reaches the bootloader.

For non-secure boot, PAMU's are already bypassed in the default
SoC configuration.
Signed-off-by: default avatarRuchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 4ba4a095
......@@ -426,7 +426,8 @@ ulong cpu_init_f(void)
{
ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
......@@ -458,6 +459,12 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
#if defined(CONFIG_FSL_CORENET)
/* Put PAMU in bypass mode */
out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
#endif
#endif
#ifdef CONFIG_CPM2
......
......@@ -1912,6 +1912,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
#define FSL_CORENET_PAMU_BYPASS 0xffff0000
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
......
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