Commit 7e44f2b7 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Kumar Gala

sbc8548: Make enabling SPD RAM configuration work

Previously, SPD configuration of RAM was non functional on
this board.  Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.

We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled.  We can revisit this dependency as the
hardware workaround becomes available.

Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.

This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.

The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs.  But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: default avatarPaul Gortmaker <>
Signed-off-by: default avatarKumar Gala <>
parent 5f4c6f0d
......@@ -59,8 +59,13 @@ struct law_entry law_table[] = {
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
int num_law_entries = ARRAY_SIZE(law_table);
......@@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 2, BOOKE_PAGESZ_64M, 1),
* TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
......@@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 4, BOOKE_PAGESZ_64M, 1),
* TLB 5: 16M Cacheable, non-guarded
......@@ -62,6 +62,27 @@ a 33MHz PCI configuration is currently untested.)
02.00.00 0x1148 0x9e00 Network controller 0x00
Memory Size and using SPD:
The default configuration uses hard coded memory configuration settings
for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
EEPROM data to read what memory is installed.
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
that the SPD data can not be read reliably.
If you want to upgrade to larger RAM size, you can simply enable
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
Note that you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.
Updating U-boot with U-boot:
......@@ -119,9 +119,15 @@
/* DDR Setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
* to collide, meaning you couldn't reliably read either. So
* physically remove the LBC PC100 SDRAM module from the board
* before enabling the two SPD options below.
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
......@@ -283,9 +289,14 @@
* SDRAM on the Local Bus (CS3 and CS4)
* Note that most boards have a hardware errata where both the
* LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
* to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
* Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
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