Commit 800c8352 authored by Marc Zyngier's avatar Marc Zyngier Committed by Albert ARIBAUD

ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: 's avatarMarc Zyngier <marc.zyngier@arm.com>
Acked-by: 's avatarIan Campbell <ijc@hellion.org.uk>
parent c19e0dd7
......@@ -46,6 +46,7 @@ _secure_monitor:
#endif
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
isb
#ifdef CONFIG_ARMV7_VIRT
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
......
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