Commit 8281c58f authored by Mingkai Hu's avatar Mingkai Hu Committed by York Sun

armv8/fsl_lsch2: Add fsl_lsch2 SoC

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarHou Zhiqiang <B48286@freescale.com>
Signed-off-by: default avatarMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: default avatarGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 9f3183d2
......@@ -14,6 +14,11 @@ obj-$(CONFIG_SPL) += spl.o
ifneq ($(CONFIG_FSL_LSCH3),)
obj-y += fsl_lsch3_speed.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
else
ifneq ($(CONFIG_FSL_LSCH2),)
obj-y += fsl_lsch2_speed.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
endif
endif
ifneq ($(CONFIG_LS2085A),)
......
#
# Copyright 2015 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
Freescale LayerScape with Chassis Generation 2
This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
for example LS1043A.
......@@ -180,6 +180,8 @@ static inline void early_mmu_setup(void)
set_pgtable_table(level1_table0,
CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
level2_table1);
#elif defined(CONFIG_FSL_LSCH2)
set_pgtable_table(level1_table0, 1, level2_table1);
#endif
/* Find the table and fill in the block entries */
for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
......@@ -215,6 +217,9 @@ static inline void early_mmu_setup(void)
*
* For LSCH3:
* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
* For LSCH2:
* Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
* Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
*/
static inline void final_mmu_setup(void)
{
......@@ -225,6 +230,9 @@ static inline void final_mmu_setup(void)
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
#ifdef CONFIG_FSL_LSCH3
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
#elif defined(CONFIG_FSL_LSCH2)
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
#endif
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
......@@ -239,6 +247,11 @@ static inline void final_mmu_setup(void)
set_pgtable_table(level1_table0,
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
level2_table1);
#elif defined(CONFIG_FSL_LSCH2)
set_pgtable_table(level1_table0, 1, level2_table1);
set_pgtable_table(level1_table0,
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
level2_table2);
#endif
/* Find the table and fill in the block entries */
......
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
#endif
return !!ret;
}
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]);
int i;
switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1
case FSL_SRDS_1:
cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
#endif
default:
printf("invalid SerDes%d\n", sd);
break;
}
/* Is serdes enabled at all? */
if (unlikely(cfg == 0))
return -ENODEV;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_get_prtcl(sd, cfg, i) == device)
return i;
}
return -ENODEV;
}
int get_serdes_protocol(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
return cfg;
}
const char *serdes_clock_to_string(u32 clock)
{
switch (clock) {
case SRDS_PLLCR0_RFCK_SEL_100:
return "100";
case SRDS_PLLCR0_RFCK_SEL_125:
return "125";
case SRDS_PLLCR0_RFCK_SEL_156_25:
return "156.25";
default:
return "100";
}
}
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else
serdes_prtcl_map[lane_prtcl] = 1;
}
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
}
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <fsl_ifc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#endif
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */
[1] = 0, /* CC1 PPL / 2 */
[4] = 1, /* CC2 PPL / 1 */
[5] = 1, /* CC2 PPL / 2 */
};
const u8 core_cplx_pll_div[8] = {
[0] = 1, /* CC1 PPL / 1 */
[1] = 2, /* CC1 PPL / 2 */
[4] = 1, /* CC2 PPL / 1 */
[5] = 2, /* CC2 PPL / 2 */
};
uint i;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
#endif
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
if (ratio[i] > 4)
freq_c_pll[i] = sysclk * ratio[i];
else
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
& 0xf;
u32 cplx_pll = core_cplx_pll[c_pll_sel];
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#if defined(CONFIG_FSL_IFC)
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}
int get_clocks(void)
{
struct sys_info sys_info;
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
if (gd->cpu_clk != 0)
return 0;
else
return 1;
}
ulong get_bus_freq(ulong dummy)
{
return gd->bus_clk;
}
ulong get_ddr_freq(ulong dummy)
{
return gd->mem_clk;
}
int get_serial_clock(void)
{
return gd->bus_clk;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0);
case MXC_DSPI_CLK:
return get_bus_freq(0);
case MXC_UART_CLK:
return get_bus_freq(0);
default:
printf("Unsupported clock\n");
}
return 0;
}
......@@ -76,6 +76,23 @@ void fsl_lsch3_early_init_f(void)
init_early_memctl_regs(); /* tighten IFC timing */
erratum_a009203();
}
#elif defined(CONFIG_LS1043A)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
......
......@@ -89,6 +89,53 @@
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define SRDS_MAX_LANES 4
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE
#define CONFIG_SYS_FSL_SEC_LE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#else
#error SoC not defined
#endif
......
......@@ -11,6 +11,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
......@@ -73,6 +74,28 @@ static struct cpu_type cpu_type_list[] = {
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif
struct sys_mmu_table {
......@@ -110,6 +133,19 @@ static const struct sys_mmu_table early_mmu_table[] = {
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#endif
};
......@@ -156,6 +192,34 @@ static const struct sys_mmu_table final_mmu_table[] = {
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#endif
};
#endif
......
......@@ -55,6 +55,92 @@ enum srds {
FSL_SRDS_1 = 0,
FSL_SRDS_2 = 1,
};
#elif defined(CONFIG_LS1043A)
enum srds_prtcl {
NONE = 0,
PCIE1,
PCIE2,
PCIE3,
PCIE4,
SATA1,
SATA2,
SRIO1,
SRIO2,
SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC10,
SGMII_FM2_DTSEC1,
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
SGMII_FM2_DTSEC5,
SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC10,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
SGMII_TSEC4,
XAUI_FM1,
XAUI_FM2,
AURORA,
CPRI1,
CPRI2,
CPRI3,
CPRI4,
CPRI5,
CPRI6,
CPRI7,
CPRI8,
XAUI_FM1_MAC9,
XAUI_FM1_MAC10,
XAUI_FM2_MAC9,
XAUI_FM2_MAC10,
HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10,
HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10,
QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
QSGMII_FM2_A,
QSGMII_FM2_B,
XFI_FM1_MAC1,
XFI_FM1_MAC2,
XFI_FM1_MAC9,
XFI_FM1_MAC10,
XFI_FM2_MAC9,
XFI_FM2_MAC10,
INTERLAKEN,
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
QSGMII_SW1_B,
SGMII_2500_FM1_DTSEC1,
SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC3,
SGMII_2500_FM1_DTSEC4,
SGMII_2500_FM1_DTSEC5,
SGMII_2500_FM1_DTSEC6,
SGMII_2500_FM1_DTSEC9,
SGMII_2500_FM1_DTSEC10,
SGMII_2500_FM2_DTSEC1,
SGMII_2500_FM2_DTSEC2,
SGMII_2500_FM2_DTSEC3,
SGMII_2500_FM2_DTSEC4,
SGMII_2500_FM2_DTSEC5,
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
SERDES_PRCTL_COUNT
};
enum srds {
FSL_SRDS_1 = 0,
};
#endif
int is_serdes_configured(enum srds_prtcl device);
......@@ -63,4 +149,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
#ifdef CONFIG_LS1043A
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif
#endif /* __FSL_SERDES_H__ */
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/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
CSU_CSLX_MG2TPR_IP,
CSU_CSLX_IFC_MEM,
CSU_CSLX_OCRAM,
CSU_CSLX_GIC,
CSU_CSLX_PCIE1,
CSU_CSLX_OCRAM2,
CSU_CSLX_QSPI_MEM,
CSU_CSLX_PCIE2,
CSU_CSLX_SATA,
CSU_CSLX_USB1,
CSU_CSLX_QM_BM_SWPORTAL,
CSU_CSLX_PCIE3 = 16,
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
CSU_CSLX_LPUART1,
CSU_CSLX_LPUART4,
CSU_CSLX_LPUART3,
CSU_CSLX_LPUART6,
CSU_CSLX_LPUART5,
CSU_CSLX_DSPI1 = 41,
CSU_CSLX_QSPI,
CSU_CSLX_ESDHC,
CSU_CSLX_IFC = 45,
CSU_CSLX_I2C1,
CSU_CSLX_I2C3 = 48,
CSU_CSLX_I2C2,
CSU_CSLX_DUART2 = 50,
CSU_CSLX_DUART1,
CSU_CSLX_WDT2,
CSU_CSLX_WDT1,
CSU_CSLX_EDMA,
CSU_CSLX_SYS_CNT,
CSU_CSLX_DMA_MUX2,
CSU_CSLX_DMA_MUX1,
CSU_CSLX_DDR,
CSU_CSLX_QUICC,
CSU_CSLX_DCFG_CCU_RCPM = 60,
CSU_CSLX_SECURE_BOOTROM,
CSU_CSLX_SFP,
CSU_CSLX_TMU,
CSU_CSLX_SECURE_MONITOR,
CSU_CSLX_SCFG,
CSU_CSLX_FM = 66,
CSU_CSLX_SEC5_5,
CSU_CSLX_BM,
CSU_CSLX_QM,
CSU_CSLX_GPIO2 = 70,
CSU_CSLX_GPIO1,
CSU_CSLX_GPIO4,
CSU_CSLX_GPIO3,
CSU_CSLX_PLATFORM_CONT,
CSU_CSLX_CSU,
CSU_CSLX_IIC4 = 77,
CSU_CSLX_WDT4,
CSU_CSLX_WDT3,
CSU_CSLX_WDT5 = 81,
CSU_CSLX_FTM2 = 86,
CSU_CSLX_FTM1,
CSU_CSLX_FTM4,
CSU_CSLX_FTM3,
CSU_CSLX_FTM6 = 90,
CSU_CSLX_FTM5,
CSU_CSLX_FTM8,
CSU_CSLX_FTM7,
CSU_CSLX_DSCR = 121,
};
static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
{CSU_CSLX_OCRAM, CSU_ALL_RW},
{CSU_CSLX_GIC, CSU_ALL_RW},
{CSU_CSLX_PCIE1, CSU_ALL_RW},
{CSU_CSLX_OCRAM2, CSU_ALL_RW},
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
{CSU_CSLX_PCIE2, CSU_ALL_RW},
{CSU_CSLX_SATA, CSU_ALL_RW},
{CSU_CSLX_USB1, CSU_ALL_RW},
{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
{CSU_CSLX_PCIE3, CSU_ALL_RW},
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
{CSU_CSLX_LPUART1, CSU_ALL_RW},
{CSU_CSLX_LPUART4, CSU_ALL_RW},
{CSU_CSLX_LPUART3, CSU_ALL_RW},
{CSU_CSLX_LPUART6, CSU_ALL_RW},
{CSU_CSLX_LPUART5, CSU_ALL_RW},
{CSU_CSLX_DSPI1, CSU_ALL_RW},
{CSU_CSLX_QSPI, CSU_ALL_RW},
{CSU_CSLX_ESDHC, CSU_ALL_RW},
{CSU_CSLX_IFC, CSU_ALL_RW},
{CSU_CSLX_I2C1, CSU_ALL_RW},
{CSU_CSLX_I2C3, CSU_ALL_RW},
{CSU_CSLX_I2C2, CSU_ALL_RW},
{CSU_CSLX_DUART2, CSU_ALL_RW},
{CSU_CSLX_DUART1, CSU_ALL_RW},
{CSU_CSLX_WDT2, CSU_ALL_RW},
{CSU_CSLX_WDT1, CSU_ALL_RW},
{CSU_CSLX_EDMA, CSU_ALL_RW},
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
{CSU_CSLX_DDR, CSU_ALL_RW},