Commit 8626cb80 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tom Rini

ARM: k2e/l: Apply WA for selecting PA clock source

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: 's avatarVitaly Andrianov <vitalya@ti.com>
Tested-by: 's avatarVitaly Andrianov <vitalya@ti.com>
Signed-off-by: 's avatarLokesh Vutla <lokeshvutla@ti.com>
parent b9f06b36
......@@ -33,6 +33,11 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
inline void pll_pa_clk_sel(void)
{
setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
}
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
......@@ -180,9 +185,8 @@ void configure_secondary_pll(const struct pll_init_data *data)
sdelay(21000);
/* Select the Output of PASS PLL as input to PASS */
if (data->pll == PASS_PLL)
setbits_le32(keystone_pll_regs[data->pll].reg1,
CFG_PLLCTL1_PAPLL_MASK);
if (data->pll == PASS_PLL && cpu_is_k2hk())
pll_pa_clk_sel();
/* Select the Output of ARM PLL as input to ARM */
if (data->pll == TETRIS_PLL)
......
......@@ -118,6 +118,7 @@ unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
void pll_pa_clk_sel(void);
#endif
#endif
......@@ -14,6 +14,7 @@
#include <fdt_support.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/ti-aemif.h>
#include <asm/ti-common/keystone_net.h>
......@@ -81,6 +82,9 @@ int board_eth_init(bd_t *bis)
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -1;
if (cpu_is_k2e() || cpu_is_k2l())
pll_pa_clk_sel();
port_num = get_num_eth_ports();
for (j = 0; j < port_num; j++) {
......
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