Commit 867f0304 authored by pekon gupta's avatar pekon gupta Committed by Tom Rini

am335x: update README for BCH16

updates documentation with explanation on how to select ECC schemes.
Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
parent 46840f66
......@@ -249,6 +249,48 @@ Platform specific options
8-bit BCH code with
- ecc calculation using GPMC hardware engine,
- error detection using ELM hardware engine.
OMAP_ECC_BCH16_CODE_HW
16-bit BCH code with
- ecc calculation using GPMC hardware engine,
- error detection using ELM hardware engine.
How to select ECC scheme on OMAP and AMxx platforms ?
-----------------------------------------------------
Though higher ECC schemes have more capability to detect and correct
bit-flips, but still selection of ECC scheme is dependent on following
- hardware engines present in SoC.
Some legacy OMAP SoC do not have ELM h/w engine thus such
SoC cannot support BCHx_HW ECC schemes.
- size of OOB/Spare region
With higher ECC schemes, more OOB/Spare area is required to
store ECC. So choice of ECC scheme is limited by NAND oobsize.
In general following expression can help:
NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
where
NAND_OOBSIZE = number of bytes available in
OOB/spare area per NAND page.
NAND_PAGESIZE = bytes in main-area of NAND page.
ECC_BYTES = number of ECC bytes generated to
protect 512 bytes of data, which is:
3 for HAM1_xx ecc schemes
7 for BCH4_xx ecc schemes
14 for BCH8_xx ecc schemes
26 for BCH16_xx ecc schemes
example to check for BCH16 on 2K page NAND
NAND_PAGESIZE = 2048
NAND_OOBSIZE = 64
2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
Thus BCH16 cannot be supported on 2K page NAND.
However, for 4K pagesize NAND
NAND_PAGESIZE = 4096
NAND_OOBSIZE = 64
ECC_BYTES = 26
2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
Thus BCH16 can be supported on 4K page NAND.
NOTE:
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