Commit 8a6553cd authored by Ye Li's avatar Ye Li Committed by Jason Liu

MLK-16198-4 imx8qm/qxp: Update ARM2 boards to support xhci and ehci at same time

When using DM xhci and ehci drivers, we can support both two controllers
(OTG and USB3) at same time. Refactor the QM and QXP ARM2 board codes and
configurations to enable them.

Because the xhci-imx8 driver will initialize the clock, and DM framework
will enable power domains, so only keep the power up in board level codes
for non-DM driver.
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Reviewed-by: default avatarPeng Fan <peng@nxp.com>
parent 6d867ff5
......@@ -355,6 +355,10 @@
status = "okay";
};
&usb2 {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
......
......@@ -71,6 +71,8 @@
mmc2 = &usdhc3;
usb0 = &usbotg1;
usbphy0 = &usbphy1;
usb1 = &usb2;
usbphy1 = &usb2_phy;
spi0 = &flexspi0;
};
......@@ -2256,6 +2258,20 @@
power-domains = <&pd_conn_usbotg0>;
};
usb2_phy: phy@0x5b160000 {
compatible = "fsl,imx8-usb-phy";
reg = <0x0 0x5b160000 0x0 0x10000>;
power-domains = <&pd_conn_usb2_phy>;
};
usb2: usb@0x5b110000 {
compatible = "fsl,imx8-usb3";
reg = <0x0 0x5b110000 0x0 0x38000>;
fsl,usbphy = <&usb2_phy>;
status = "disabled";
power-domains = <&pd_conn_usb2>;
};
ddr_pmu0: ddr_pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x0 0x5c020000 0x0 0x10000>;
......
......@@ -418,3 +418,7 @@
adp-disable;
status = "okay";
};
&usb2 {
status = "okay";
};
\ No newline at end of file
......@@ -66,6 +66,9 @@
mmc2 = &usdhc3;
spi0 = &flexspi0;
usb0 = &usbotg1;
usbphy0 = &usbphy1;
usb1 = &usb2;
usbphy1 = &usb2_phy;
};
memory@80000000 {
......@@ -1447,6 +1450,20 @@
power-domains = <&pd_conn_usbotg0>;
};
usb2_phy: phy@0x5b160000 {
compatible = "fsl,imx8-usb-phy";
reg = <0x0 0x5b160000 0x0 0x10000>;
power-domains = <&pd_conn_usb2_phy>;
};
usb2: usb@0x5b110000 {
compatible = "fsl,imx8-usb3";
reg = <0x0 0x5b110000 0x0 0x38000>;
fsl,usbphy = <&usb2_phy>;
status = "disabled";
power-domains = <&pd_conn_usb2>;
};
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
reg = <0x0 0x5a8d0000 0x0 0x10000>;
......
......@@ -585,14 +585,10 @@ int is_recovery_key_pressing(void)
/* Only Enable USB3 resources currently */
int board_usb_init(int index, enum usb_init_type init)
{
sc_err_t err;
sc_ipc_t ipc;
sc_rsrc_t usbs[2] = {SC_R_USB_2, SC_R_USB_2_PHY};
#ifndef CONFIG_DM_USB
struct power_domain pd;
int ret;
ipc = gd->arch.ipc_channel_handle;
/* Power on usb */
if (!power_domain_lookup_name("conn_usb2", &pd)) {
ret = power_domain_on(&pd);
......@@ -605,21 +601,7 @@ int board_usb_init(int index, enum usb_init_type init)
if (ret)
printf("conn_usb2_phy Power up failed! (error = %d)\n", ret);
}
err = sc_pm_clock_enable(ipc, usbs[0], SC_PM_CLK_MISC, true, false);
if (err != SC_ERR_NONE)
printf("USB3 set clock failed!, line=%d (error = %d)\n",
__LINE__, err);
err = sc_pm_clock_enable(ipc, usbs[0], SC_PM_CLK_MST_BUS, true, false);
if (err != SC_ERR_NONE)
printf("USB3 set clock failed!, line=%d (error = %d)\n",
__LINE__, err);
err = sc_pm_clock_enable(ipc, usbs[0], SC_PM_CLK_PER, true, false);
if (err != SC_ERR_NONE)
printf("USB3 set clock failed!, line=%d (error = %d)\n",
__LINE__, err);
#endif
return 0;
}
......
......@@ -571,6 +571,30 @@ int is_recovery_key_pressing(void)
#endif /*CONFIG_ANDROID_RECOVERY*/
#endif /*CONFIG_FSL_FASTBOOT*/
/* Only Enable USB3 resources currently */
int board_usb_init(int index, enum usb_init_type init)
{
#ifndef CONFIG_DM_USB
struct power_domain pd;
int ret;
/* Power on usb */
if (!power_domain_lookup_name("conn_usb2", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("conn_usb2 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("conn_usb2_phy", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("conn_usb2_phy Power up failed! (error = %d)\n", ret);
}
#endif
return 0;
}
#if defined(CONFIG_VIDEO_IMXDPUV1)
static void enable_lvds(struct display_info_t const *dev)
{
......
......@@ -18,8 +18,8 @@ CONFIG_CMD_I2C=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
#CONFIG_DM_USB is not set
#CONFIG_USB_EHCI_HCD is not set
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
......
......@@ -18,8 +18,8 @@ CONFIG_CMD_I2C=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
#CONFIG_DM_USB is not set
#CONFIG_USB_EHCI_HCD is not set
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
......
......@@ -15,10 +15,14 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
......
......@@ -15,10 +15,14 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
......
......@@ -14,10 +14,14 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
......
......@@ -288,9 +288,10 @@
/* USB Config */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* USB 3.0 controller configs */
#ifdef CONFIG_USB_XHCI_IMX8
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
......@@ -300,17 +301,17 @@
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif
#endif /* CONFIG_CMD_USB */
#ifdef CONFIG_USB_GADGET
#define CONFIG_USBD_HS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
#if defined(CONFIG_ANDROID_SUPPORT)
#include "imx8qm_arm2_android.h"
#endif
#endif /* CONFIG_CMD_USB */
/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IMXDPUV1
......
......@@ -290,12 +290,22 @@
#define CONFIG_APBH_DMA_BURST8
#endif
/* USB OTG controller configs */
/* USB Config */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* USB 3.0 controller configs */
#ifdef CONFIG_USB_XHCI_IMX8
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/* USB OTG controller configs */
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif
#endif /* CONFIG_CMD_USB */
#ifdef CONFIG_USB_GADGET
#define CONFIG_USBD_HS
......
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