Commit 8bef9dae authored by fang hui's avatar fang hui Committed by Luo Ji

MA-10071 [iot] Add board support imx7d multa

Add board support imx7d multa

Change-Id: I5c50363681d7cb1d93bf8d8a14d93496bd152bcb
Signed-off-by: 's avatarfang hui <hui.fang@nxp.com>
parent 6ccbd3bc
......@@ -36,6 +36,12 @@ config TARGET_PICO_IMX7D
select DM
select DM_THERMAL
config TARGET_MULTA_IMX7D
bool "Support multa-imx7d"
select MX7D
select DM
select DM_THERMAL
config TARGET_MX7D_12X12_DDR3_ARM2
bool "Support mx7d_12x12_ddr3_arm2"
select BOARD_LATE_INIT
......@@ -89,6 +95,7 @@ source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
source "board/freescale/pico-imx7d/Kconfig"
source "board/freescale/multa-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"
......
if TARGET_MULTA_IMX7D
config SYS_BOARD
default "multa-imx7d"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "multa-imx7d"
endif
MULTA IMX7D BOARD
M: Fang Hui <hui.fang@nxp.com>
S: Maintained
F: board/freescale/multa-imx7d
F: include/configs/multa-imx7d.h
F: configs/multa-imx7d_defconfig
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := multa-imx7d.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/multa-imx7d/plugin.bin 0x00910000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x30340004 0x4F400005
/* Clear then set bit30 to ensure exit from DDR retention */
DATA 4 0x30360388 0x40000000
DATA 4 0x30360384 0x40000000
DATA 4 0x30391000 0x00000002
DATA 4 0x307a0000 0x01040001
DATA 4 0x307a01a0 0x80400003
DATA 4 0x307a01a4 0x00100020
DATA 4 0x307a01a8 0x80100004
DATA 4 0x307a0064 0x00400046
DATA 4 0x307a0490 0x00000001
DATA 4 0x307a00d0 0x00020083
DATA 4 0x307a00d4 0x00690000
DATA 4 0x307a00dc 0x09300004
DATA 4 0x307a00e0 0x04080000
DATA 4 0x307a00e4 0x00100004
DATA 4 0x307a00f4 0x0000033f
DATA 4 0x307a0100 0x09081109
DATA 4 0x307a0104 0x0007020d
DATA 4 0x307a0108 0x03040407
DATA 4 0x307a010c 0x00002006
DATA 4 0x307a0110 0x04020205
DATA 4 0x307a0114 0x03030202
DATA 4 0x307a0120 0x00000803
DATA 4 0x307a0180 0x00800020
DATA 4 0x307a0184 0x02000100
DATA 4 0x307a0190 0x02098204
DATA 4 0x307a0194 0x00030303
DATA 4 0x307a0200 0x00000016
DATA 4 0x307a0204 0x00080808
DATA 4 0x307a0210 0x00000f0f
DATA 4 0x307a0214 0x07070707
DATA 4 0x307a0218 0x0f070707
DATA 4 0x307a0240 0x06000604
DATA 4 0x307a0244 0x00000001
DATA 4 0x30391000 0x00000000
DATA 4 0x30790000 0x17420f40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790010 0x00060807
DATA 4 0x307900b0 0x1010007e
DATA 4 0x3079009c 0x00000b24
DATA 4 0x30790020 0x08080808
DATA 4 0x30790030 0x08080808
DATA 4 0x30790050 0x01000010
DATA 4 0x30790050 0x00000010
DATA 4 0x307900c0 0x0e407304
DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e447306
CHECK_BITS_SET 4 0x307900c4 0x1
DATA 4 0x307900c0 0x0e407304
DATA 4 0x30384130 0x00000000
DATA 4 0x30340020 0x00000178
DATA 4 0x30384130 0x00000002
DATA 4 0x30790018 0x0000000f
CHECK_BITS_SET 4 0x307a0004 0x1
#endif
This diff is collapsed.
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* DDR script */
.macro imx7d_ddrphy_latency_setting
ldr r2, =ANATOP_BASE_ADDR
ldr r3, [r2, #0x800]
and r3, r3, #0xFF
cmp r3, #0x11
bne NO_DELAY
/*TO 1.1*/
ldr r1, =0x00000dee
str r1, [r0, #0x9c]
ldr r1, =0x18181818
str r1, [r0, #0x7c]
ldr r1, =0x18181818
str r1, [r0, #0x80]
ldr r1, =0x40401818
str r1, [r0, #0x84]
ldr r1, =0x00000040
str r1, [r0, #0x88]
ldr r1, =0x40404040
str r1, [r0, #0x6c]
b TUNE_END
NO_DELAY:
/*TO 1.0*/
ldr r1, =0x00000b24
str r1, [r0, #0x9c]
TUNE_END:
.endm
.macro imx7d_ddr_freq_setting
ldr r2, =ANATOP_BASE_ADDR
ldr r3, [r2, #0x800]
and r3, r3, #0xFF
cmp r3, #0x11
bne FREQ_DEFAULT_533
/* Change to 400Mhz for TO1.1 */
ldr r0, =ANATOP_BASE_ADDR
ldr r1, =0x70
ldr r2, =0x00703021
str r2, [r0, r1]
ldr r1, =0x90
ldr r2, =0x0
str r2, [r0, r1]
ldr r1, =0x70
ldr r2, =0x00603021
str r2, [r0, r1]
ldr r3, =0x80000000
wait_lock:
ldr r2, [r0, r1]
and r2, r3
cmp r2, r3
bne wait_lock
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x9880
ldr r2, =0x1
str r2, [r0, r1]
FREQ_DEFAULT_533:
.endm
.macro imx7d_multa_ddr_setting
imx7d_ddr_freq_setting
/* Configure ocram_epdc */
ldr r0, =IOMUXC_GPR_BASE_ADDR
ldr r1, =0x4f400005
str r1, [r0, #0x4]
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
ldr r0, =ANATOP_BASE_ADDR
ldr r1, =(0x1 << 30)
str r1, [r0, #0x388]
str r1, [r0, #0x384]
ldr r0, =SRC_BASE_ADDR
ldr r1, =0x2
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRC_IPS_BASE_ADDR
ldr r1, =0x01040001
str r1, [r0]
ldr r1, =0x80400003
str r1, [r0, #0x1a0]
ldr r1, =0x00100020
str r1, [r0, #0x1a4]
ldr r1, =0x80100004
str r1, [r0, #0x1a8]
ldr r1, =0x00400046
str r1, [r0, #0x64]
ldr r1, =0x1
str r1, [r0, #0x490]
ldr r1, =0x00020001
str r1, [r0, #0xd0]
ldr r1, =0x00690000
str r1, [r0, #0xd4]
ldr r1, =0x09300004
str r1, [r0, #0xdc]
ldr r1, =0x04080000
str r1, [r0, #0xe0]
ldr r1, =0x00100004
str r1, [r0, #0xe4]
ldr r1, =0x33f
str r1, [r0, #0xf4]
ldr r1, =0x09081109
str r1, [r0, #0x100]
ldr r1, =0x0007020d
str r1, [r0, #0x104]
ldr r1, =0x03040407
str r1, [r0, #0x108]
ldr r1, =0x00002006
str r1, [r0, #0x10c]
ldr r1, =0x04020205
str r1, [r0, #0x110]
ldr r1, =0x03030202
str r1, [r0, #0x114]
ldr r1, =0x00000803
str r1, [r0, #0x120]
ldr r1, =0x00800020
str r1, [r0, #0x180]
ldr r1, =0x02000100
str r1, [r0, #0x184]
ldr r1, =0x02098204
str r1, [r0, #0x190]
ldr r1, =0x00030303
str r1, [r0, #0x194]
ldr r1, =0x00000016
str r1, [r0, #0x200]
ldr r1, =0x00080808
str r1, [r0, #0x204]
ldr r1, =0x00000f0f
str r1, [r0, #0x210]
ldr r1, =0x07070707
str r1, [r0, #0x214]
ldr r1, =0x0f070707
str r1, [r0, #0x218]
ldr r1, =0x06000604
str r1, [r0, #0x240]
ldr r1, =0x00000001
str r1, [r0, #0x244]
ldr r0, =SRC_BASE_ADDR
mov r1, #0x0
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRPHY_IPS_BASE_ADDR
ldr r1, =0x17420f40
str r1, [r0]
ldr r1, =0x10210100
str r1, [r0, #0x4]
ldr r1, =0x00060807
str r1, [r0, #0x10]
ldr r1, =0x1010007e
str r1, [r0, #0xb0]
imx7d_ddrphy_latency_setting
ldr r1, =0x08080808
str r1, [r0, #0x20]
ldr r1, =0x08080808
str r1, [r0, #0x30]
ldr r1, =0x01000010
str r1, [r0, #0x50]
ldr r1, =0x0e407304
str r1, [r0, #0xc0]
ldr r1, =0x0e447304
str r1, [r0, #0xc0]
ldr r1, =0x0e447306
str r1, [r0, #0xc0]
wait_zq:
ldr r1, [r0, #0xc4]
tst r1, #0x1
beq wait_zq
ldr r1, =0x0e407304
str r1, [r0, #0xc0]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x0
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =IOMUXC_GPR_BASE_ADDR
mov r1, #0x178
str r1, [r0, #0x20]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x2
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =DDRPHY_IPS_BASE_ADDR
ldr r1, =0x0000000f
str r1, [r0, #0x18]
ldr r0, =DDRC_IPS_BASE_ADDR
wait_stat:
ldr r1, [r0, #0x4]
tst r1, #0x1
beq wait_stat
.endm
.macro imx7_clock_gating
.endm
.macro imx7_qos_setting
.endm
.macro imx7_ddr_setting
imx7d_multa_ddr_setting
.endm
/* include the common plugin code here */
#include <asm/arch/mx7_plugin.S>
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/multa-imx7d/imximage.cfg,MX7D,ANDROID_THINGS_SUPPORT"
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_TARGET_MULTA_IMX7D=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_BOOTDELAY=3
CONFIG_EFI_PARTITION=y
CONFIG_VIDEO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
This diff is collapsed.
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MULTA_IMX7D_ANDROIDTHINGS_H
#define __MULTA_IMX7D_ANDROIDTHINGS_H
#define TRUSTY_OS_ENTRY 0x9e000000
#define TRUSTY_OS_RAM_SIZE 0x2000000
#define TEE_HWPARTITION_ID 2
#define TRUSTY_OS_MMC_BLKS 0xFFF
#ifdef CONFIG_IMX_TRUSTY_OS
#define NON_SECURE_FASTBOOT
#define TRUSTY_KEYSLOT_PACKAGE
#endif
#include "mx_android_common.h"
/* For NAND we don't support lock/unlock */
#ifndef CONFIG_NAND_BOOT
#define CONFIG_FASTBOOT_LOCK
#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
#define FSL_FASTBOOT_FB_DEV "mmc"
#endif
#define CONFIG_ANDROID_AB_SUPPORT
#define FASTBOOT_ENCRYPT_LOCK
#define CONFIG_FSL_CAAM_KB
#define CONFIG_SHA1
#define CONFIG_SHA256
#ifdef CONFIG_SYS_MMC_ENV_DEV
#undef CONFIG_SYS_MMC_ENV_DEV
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#endif
#ifdef CONFIG_SYS_MMC_ENV_PART
#undef CONFIG_SYS_MMC_ENV_PART
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */
#endif
#define CONFIG_SYSTEM_RAMDISK_SUPPORT
#define CONFIG_AVB_SUPPORT
#ifdef CONFIG_AVB_SUPPORT
#define CONFIG_SUPPORT_EMMC_RPMB
#ifdef CONFIG_SYS_MALLOC_LEN
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
#endif
/* fuse bank size in word */
/* infact 7D have no enough bits
* set this size to 0 will disable
* program/read FUSE */
#define CONFIG_AVB_FUSE_BANK_SIZEW 0
#define CONFIG_AVB_FUSE_BANK_START 0
#define CONFIG_AVB_FUSE_BANK_END 0
#endif
#endif
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