Commit 8d1e3cb1 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support

These boards are still non-generic boards.
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
parent 3b95288a
......@@ -41,12 +41,6 @@ config TARGET_MPC8349EMDS
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
config TARGET_MPC8360EMDS
bool "Support MPC8360EMDS"
config TARGET_MPC8360ERDK
bool "Support MPC8360ERDK"
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
......@@ -81,8 +75,6 @@ source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
source "board/freescale/mpc8360emds/Kconfig"
source "board/freescale/mpc8360erdk/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
......
......@@ -63,7 +63,7 @@ int pib_init(void)
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
#if defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
......
if TARGET_MPC8360EMDS
config SYS_BOARD
default "mpc8360emds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8360EMDS"
endif
MPC8360EMDS BOARD
M: Dave Liu <daveliu@freescale.com>
S: Maintained
F: board/freescale/mpc8360emds/
F: include/configs/MPC8360EMDS.h
F: configs/MPC8360EMDS_33_defconfig
F: configs/MPC8360EMDS_33_ATM_defconfig
F: configs/MPC8360EMDS_33_HOST_33_defconfig
F: configs/MPC8360EMDS_33_HOST_66_defconfig
F: configs/MPC8360EMDS_33_SLAVE_defconfig
F: configs/MPC8360EMDS_66_defconfig
F: configs/MPC8360EMDS_66_ATM_defconfig
F: configs/MPC8360EMDS_66_HOST_33_defconfig
F: configs/MPC8360EMDS_66_HOST_66_defconfig
F: configs/MPC8360EMDS_66_SLAVE_defconfig
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += mpc8360emds.o
obj-$(CONFIG_PCI) += pci.o
Freescale MPC8360EMDS Board
-----------------------------------------
1. Board Switches and Jumpers
1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
For some reason, the HW designers describe the switch settings
in terms of 0 and 1, and then map that to physical switches where
the label "On" refers to logic 0 and "Off" is logic 1.
Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
bits may contribute to signals that are numbered based at 0,
and some of those signals may be high-bit-number-0 too. Heed
well the names and labels and do not get confused.
"Off" == 1
"On" == 0
SW18 is switch 18 as silk-screened onto the board.
SW4[8] is the bit labeled 8 on Switch 4.
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
and bits labeled 8 is set as "Off".
1.1 There are three type boards for MPC8360E silicon up to now, They are
* MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
* MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
* MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
1.2 For all the MPC8360EMDS Board
First, make sure the board default setting is consistent with the
document shipped with your board. Then apply the following setting:
SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
SW4[1-8]= 0011_0000 (Flash boot on local bus)
SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
SW10[1-8]= 0000_1000 (core PLL setting)
SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
JP6 1-2
on board Oscillator: 66M
1.3 Since different board/chip rev. combinations have AC timing issues,
u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
When the rev2.x silicon mount on these boards, and if you are using
u-boot version after this patch, to make the ethernet interfaces usable,
and to enable RGMII-ID on your board, you have to setup the jumpers
correctly.
* MPC8360E-MDS-PB PROTO
nothing to do
* MPC8360E-MDS-PB PILOT
JP9 and JP8 should be ON
* MPC8360EA-MDS-PB PROTO
JP2 and JP3 should be ON
2. Memory Map
2.1. The memory map should look pretty much like this:
0x0000_0000 0x7fff_ffff DDR 2G
0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
0xc000_0000 0xdfff_ffff Empty 512M
0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
0xe020_0000 0xe02f_ffff Empty 1M
0xe030_0000 0xe03f_ffff PCI IO 1M
0xe040_0000 0xefff_ffff Empty 252M
0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
0xf400_0000 0xf7ff_ffff Empty 64M
0xf800_0000 0xf800_7fff BCSR on CS1 32K
0xf800_8000 0xf800_ffff PIB CS4 32K
0xf801_0000 0xf801_7fff PIB CS5 32K
0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
3. Definitions
3.1 Explanation of NEW definitions in:
include/configs/MPC8360EMDS.h
CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
CONFIG_MPC8360 MPC8360 specific
CONFIG_MPC8360EMDS MPC8360EMDS board specific
4. Compilation
MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
Assuming you're using BASH shell:
export CROSS_COMPILE=your-cross-compile-prefix
cd u-boot
make distclean
make MPC8360EMDS_XX_config
make
MPC8360EMDS support ATM, PCI in host and slave mode.
To make u-boot support ATM :
1) Make MPC8360EMDS_XX_ATM_config
To make u-boot support PCI host 66M :
1) DIP SW support PCI mode as described in Section 1.1.
2) Make MPC8360EMDS_XX_HOST_66_config
To make u-boot support PCI host 33M :
1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
2) Make MPC8360EMDS_XX_HOST_33_config
To make u-boot support PCI slave 66M :
1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
2) Make MPC8360EMDS_XX_SLAVE_config
(where XX is:
33 - 33.33MHz oscillator
66 - 66MHz oscillator)
5. Downloading and Flashing Images
5.0 Download over serial line using Kermit:
loadb
[Drop to kermit:
^\c
send <u-boot-bin-image>
c
]
Or via tftp:
tftp 10000 u-boot.bin
5.1 Reflash U-boot Image using U-boot
tftp 20000 u-boot.bin
protect off fef00000 fef3ffff
erase fef00000 fef3ffff
cp.b 20000 fef00000 xxxx
or
cp.b 20000 fef00000 3ffff
You have to supply the correct byte count with 'xxxx' from the TFTP result log.
Maybe 3ffff will work too, that corresponds to the erased sectors.
6. Notes
1) The console baudrate for MPC8360EMDS is 115200bps.
This diff is collapsed.
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* PCI Configuration space access support for MPC83xx PCI Bridge
*/
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#ifdef CONFIG_MPC83XX_PCI2
static struct pci_region pci2_regions[] = {
{
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
size: CONFIG_SYS_PCI2_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI2_IO_BASE,
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
size: CONFIG_SYS_PCI2_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
size: CONFIG_SYS_PCI2_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#endif
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
struct pci_region *reg[] = { pci1_regions };
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
mpc83xx_pci_init(1, reg);
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].pitar0 = 0x0;
pci_ctrl[0].pibar0 = 0x0;
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 &= ~PIWAR_EN;
pci_ctrl[0].pitar2 = 0x0;
pci_ctrl[0].pibar2 = 0x0;
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
/* Unlock the configuration bit */
mpc83xx_pcislave_unlock(0);
printf("PCI: Agent mode enabled\n");
}
#else
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
#ifndef CONFIG_MPC83XX_PCI2
struct pci_region *reg[] = { pci1_regions };
#else
struct pci_region *reg[] = { pci1_regions, pci2_regions };
#endif
/* initialize the PCA9555PW IO expander on the PIB board */
pib_init();
#if defined(CONFIG_PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#elif defined(CONFIG_PCI_33M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
printf("PCI clock is 33MHz\n");
#else
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg);
#endif
}
#endif /* CONFIG_PCISLAVE */
if TARGET_MPC8360ERDK
config SYS_BOARD
default "mpc8360erdk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8360ERDK"
endif
MPC8360ERDK BOARD
#M: Anton Vorontsov <avorontsov@ru.mvista.com>
S: Orphan (since 2014-03)
F: board/freescale/mpc8360erdk/
F: include/configs/MPC8360ERDK.h
F: configs/MPC8360ERDK_defconfig
F: configs/MPC8360ERDK_33_defconfig
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += mpc8360erdk.o
obj-$(CONFIG_CMD_NAND) += nand.o
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <pci.h>
#include <libfdt.h>
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
/* UCC1 - UEC (Gigabit) */
{0, 3, 1, 0, 1}, /* TxD0 */
{0, 4, 1, 0, 1}, /* TxD1 */
{0, 5, 1, 0, 1}, /* TxD2 */
{0, 6, 1, 0, 1}, /* TxD3 */
{0, 9, 2, 0, 1}, /* RxD0 */
{0, 10, 2, 0, 1}, /* RxD1 */
{0, 11, 2, 0, 1}, /* RxD2 */
{0, 12, 2, 0, 1}, /* RxD3 */
{0, 7, 1, 0, 1}, /* TX_EN */
{0, 8, 1, 0, 1}, /* TX_ER */
{0, 15, 2, 0, 1}, /* RX_DV */
{0, 0, 2, 0, 1}, /* RX_CLK */
{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
/* UCC2 - UEC (Gigabit) */
{0, 17, 1, 0, 1}, /* TxD0 */
{0, 18, 1, 0, 1}, /* TxD1 */
{0, 19, 1, 0, 1}, /* TxD2 */
{0, 20, 1, 0, 1}, /* TxD3 */
{0, 23, 2, 0, 1}, /* RxD0 */
{0, 24, 2, 0, 1}, /* RxD1 */
{0, 25, 2, 0, 1}, /* RxD2 */
{0, 26, 2, 0, 1}, /* RxD3 */
{0, 21, 1, 0, 1}, /* TX_EN */
{0, 22, 1, 0, 1}, /* TX_ER */
{0, 29, 2, 0, 1}, /* RX_DV */
{0, 31, 2, 0, 1}, /* RX_CLK */
{2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
/* UCC7 - UEC */
{4, 0, 1, 0, 1}, /* TxD0 */
{4, 1, 1, 0, 1}, /* TxD1 */
{4, 2, 1, 0, 1}, /* TxD2 */
{4, 3, 1, 0, 1}, /* TxD3 */
{4, 6, 2, 0, 1}, /* RxD0 */
{4, 7, 2, 0, 1}, /* RxD1 */
{4, 8, 2, 0, 1}, /* RxD2 */
{4, 9, 2, 0, 1}, /* RxD3 */
{4, 4, 1, 0, 1}, /* TX_EN */
{4, 5, 1, 0, 1}, /* TX_ER */
{4, 12, 2, 0, 1}, /* RX_DV */
{4, 13, 2, 0, 1}, /* RX_ER */
{4, 10, 2, 0, 1}, /* COL */
{4, 11, 2, 0, 1}, /* CRS */
{2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
{2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
/* UCC4 - UEC */
{1, 14, 1, 0, 1}, /* TxD0 */
{1, 15, 1, 0, 1}, /* TxD1 */
{1, 16, 1, 0, 1}, /* TxD2 */
{1, 17, 1, 0, 1}, /* TxD3 */
{1, 20, 2, 0, 1}, /* RxD0 */
{1, 21, 2, 0, 1}, /* RxD1 */
{1, 22, 2, 0, 1}, /* RxD2 */
{1, 23, 2, 0, 1}, /* RxD3 */
{1, 18, 1, 0, 1}, /* TX_EN */
{1, 19, 1, 0, 2}, /* TX_ER */
{1, 26, 2, 0, 1}, /* RX_DV */
{1, 27, 2, 0, 1}, /* RX_ER */
{1, 24, 2, 0, 1}, /* COL */
{1, 25, 2, 0, 1}, /* CRS */
{2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
{2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
/* PCI1 */
{5, 4, 2, 0, 3}, /* PCI_M66EN */
{5, 5, 1, 0, 3}, /* PCI_INTA */
{5, 6, 1, 0, 3}, /* PCI_RSTO */
{5, 7, 3, 0, 3}, /* PCI_C_BE0 */
{5, 8, 3, 0, 3}, /* PCI_C_BE1 */
{5, 9, 3, 0, 3}, /* PCI_C_BE2 */
{5, 10, 3, 0, 3}, /* PCI_C_BE3 */
{5, 11, 3, 0, 3}, /* PCI_PAR */
{5, 12, 3, 0, 3}, /* PCI_FRAME */
{5, 13, 3, 0, 3}, /* PCI_TRDY */
{5, 14, 3, 0, 3}, /* PCI_IRDY */
{5, 15, 3, 0, 3}, /* PCI_STOP */
{5, 16, 3, 0, 3}, /* PCI_DEVSEL */
{5, 17, 0, 0, 0}, /* PCI_IDSEL */
{5, 18, 3, 0, 3}, /* PCI_SERR */
{5, 19, 3, 0, 3}, /* PCI_PERR */
{5, 20, 3, 0, 3}, /* PCI_REQ0 */
{5, 21, 2, 0, 3}, /* PCI_REQ1 */
{5, 22, 2, 0, 3}, /* PCI_GNT2 */
{5, 23, 3, 0, 3}, /* PCI_GNT0 */
{5, 24, 1, 0, 3}, /* PCI_GNT1 */
{5, 25, 1, 0, 3}, /* PCI_GNT2 */
{5, 26, 0, 0, 0}, /* PCI_CLK0 */
{5, 27, 0, 0, 0}, /* PCI_CLK1 */
{5, 28, 0, 0, 0}, /* PCI_CLK2 */
{5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
{6, 0, 3, 0, 3}, /* PCI_AD0 */
{6, 1, 3, 0, 3}, /* PCI_AD1 */
{6, 2, 3, 0, 3}, /* PCI_AD2 */
{6, 3, 3, 0, 3}, /* PCI_AD3 */
{6, 4, 3, 0, 3}, /* PCI_AD4 */
{6, 5, 3, 0, 3}, /* PCI_AD5 */
{6, 6, 3, 0, 3}, /* PCI_AD6 */
{6, 7, 3, 0, 3}, /* PCI_AD7 */
{6, 8, 3, 0, 3}, /* PCI_AD8 */
{6, 9, 3, 0, 3}, /* PCI_AD9 */
{6, 10, 3, 0, 3}, /* PCI_AD10 */
{6, 11, 3, 0, 3}, /* PCI_AD11 */
{6, 12, 3, 0, 3}, /* PCI_AD12 */
{6, 13, 3, 0, 3}, /* PCI_AD13 */
{6, 14, 3, 0, 3}, /* PCI_AD14 */
{6, 15, 3, 0, 3}, /* PCI_AD15 */
{6, 16, 3, 0, 3}, /* PCI_AD16 */
{6, 17, 3, 0, 3}, /* PCI_AD17 */
{6, 18, 3, 0, 3}, /* PCI_AD18 */
{6, 19, 3, 0, 3}, /* PCI_AD19 */
{6, 20, 3, 0, 3}, /* PCI_AD20 */
{6, 21, 3, 0, 3}, /* PCI_AD21 */
{6, 22, 3, 0, 3}, /* PCI_AD22 */
{6, 23, 3, 0, 3}, /* PCI_AD23 */
{6, 24, 3, 0, 3}, /* PCI_AD24 */
{6, 25, 3, 0, 3}, /* PCI_AD25 */
{6, 26, 3, 0, 3}, /* PCI_AD26 */
{6, 27, 3, 0, 3}, /* PCI_AD27 */
{6, 28, 3, 0, 3}, /* PCI_AD28 */
{6, 29, 3, 0, 3}, /* PCI_AD29 */
{6, 30, 3, 0, 3}, /* PCI_AD30 */
{6, 31, 3, 0, 3}, /* PCI_AD31 */
/* NAND */
{4, 18, 2, 0, 0}, /* NAND_RYnBY */
/* DUART - UART2 */
{5, 0, 1, 0, 2}, /* UART2_SOUT */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
/* UCC5 - UART3 */
{3, 0, 1, 0, 1}, /* UART3_TX */
{3, 4, 1, 0, 1}, /* UART3_RTS */
{3, 6, 2, 0, 1}, /* UART3_RX */
{3, 12, 2, 0, 0}, /* UART3_CTS */
{3, 13, 2, 0, 0}, /* UCC5_CD */
/* UCC6 - UART4 */
{3, 14, 1, 0, 1}, /* UART4_TX */
{3, 18, 1, 0, 1}, /* UART4_RTS */
{3, 20, 2, 0, 1}, /* UART4_RX */
{3, 26, 2, 0, 0}, /* UART4_CTS */
{3, 27, 2, 0, 0}, /* UCC6_CD */
/* Fujitsu MB86277 (MINT) graphics controller */
{0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
{1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
{1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
{2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
/* AD7843 ADC/Touchscreen controller */
{4, 14, 1, 0, 0}, /* SPI_nCS0 */
{4, 28, 3, 0, 3}, /* SPI_MOSI */
{4, 29, 3, 0, 3}, /* SPI_MISO */
{4, 30, 3, 0, 3}, /* SPI_CLK */
/* Freescale QUICC Engine USB Host Controller (FHCI) */
{1, 2, 1, 0, 3}, /* USBOE */
{1, 3, 1, 0, 3}, /* USBTP */
{1, 8, 1, 0, 1}, /* USBTN */
{1, 9, 2, 1, 3}, /* USBRP */
{1, 10, 2, 0, 3}, /* USBRXD */
{1, 11, 2, 1, 3}, /* USBRN */
{2, 20, 2, 0, 1}, /* CLK21 */
{4, 20, 1, 0, 0}, /* SPEED */
{4, 21, 1, 0, 0}, /* SUSPND */
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
};
int board_early_init_r(void)
{
void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
u32 val;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
*/
val = in_be32(reg);
/* UCC1 */
val |= 0x00003000;
/* UCC2 */
val |= 0x0c000000;
out_be32(reg, val);
return 0;
}
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
int checkboard(void)
{
puts("Board: Freescale/Logic MPC8360ERDK\n");