Commit 8d8e13e1 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Marek Vasut

arm: socfpga: enable data/inst prefetch and shared override in the L2

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
Signed-off-by: default avatarDinh Nguyen <>
parent 1275456d
......@@ -17,6 +17,8 @@
#define L2X0_CTRL_EN 1
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
struct pl310_regs {
u32 pl310_cache_id;
......@@ -52,6 +52,18 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
/* disable the L2 cache */
writel(0, &pl310->pl310_ctrl);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
* DesignWare Ethernet initialization
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