Commit 8e9c897b authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Nobuhiro Iwamatsu

sh: add support for sh7757lcr board

The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
Ethernet, and more.

This patch supports the following functions:
 - 256MB DDR3-SDRAM
 - SPI ROM
 - Ethernet
Signed-off-by: 's avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: 's avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 6639562e
......@@ -1025,6 +1025,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
R0P77570030RL SH7757
R0P77850011RL SH7785
#########################################################################
......
......@@ -44,6 +44,8 @@
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
......
/*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_CPU_SH7757_H_
#define _ASM_CPU_SH7757_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* SerMux */
#define SMR0 0xfe470000
/* TMU0 */
#define TSTR 0xFE430004
#define TOCR 0xFE430000
#define TSTR0 0xFE430004
#define TCOR0 0xFE430008
#define TCNT0 0xFE43000C
#define TCR0 0xFE430010
#define TCOR1 0xFE430014
#define TCNT1 0xFE430018
#define TCR1 0xFE43001C
#define TCOR2 0xFE430020
#define TCNT2 0xFE430024
#define TCR2 0xFE430028
#define TCPR2 0xFE43002C
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GCTRL, GRA */
struct gctrl_regs {
unsigned int wprotect;
unsigned int gplldiv;
unsigned int gracr2; /* GRA */
unsigned int gracr3; /* GRA */
unsigned int reserved[4];
unsigned int fcntcr1;
unsigned int fcntcr2;
unsigned int reserved2[2];
unsigned int gpll1div;
unsigned int vcompsel;
unsigned int reserved3[62];
unsigned int fdlmon;
unsigned int reserved4[2];
unsigned int flcrmon;
unsigned int reserved5[944];
unsigned int spibootcan;
};
#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
/* PCIe setup */
struct pcie_setup_regs {
unsigned int pbictl0;
unsigned int gradevctl;
unsigned int reserved[2];
unsigned int bmcinf[6];
unsigned int reserved2[118];
unsigned int idset[2];
unsigned int subidset;
unsigned int reserved3[2];
unsigned int linkconfset[4];
unsigned int trsid;
unsigned int reserved4[6];
unsigned int toutset;
unsigned int reserved5[7];
unsigned int lad0;
unsigned int ladmsk0;
unsigned int lad1;
unsigned int ladmsk1;
unsigned int lad2;
unsigned int ladmsk2;
unsigned int lad3;
unsigned int ladmsk3;
unsigned int lad4;
unsigned int ladmsk4;
unsigned int lad5;
unsigned int ladmsk5;
unsigned int reserved6[94];
unsigned int vdmrxvid[2];
unsigned int reserved7;
unsigned int pbiintfr;
unsigned int pbiinten;
unsigned int msimap;
unsigned int barmap;
unsigned int baracsize;
unsigned int advserest;
unsigned int pbictl3;
unsigned int reserved8[8];
unsigned int pbictl1;
unsigned int scratch0;
unsigned int reserved9[6];
unsigned int pbictl2;
unsigned int reserved10;
unsigned int pbirev;
};
#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
struct pcie_system_bus_regs {
unsigned int reserved[3];
unsigned int endictl0;
unsigned int endictl1;
};
#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
/* PCIe-Bridge */
struct pciebrg_regs {
unsigned short ctrl_h8s;
unsigned short reserved[7];
unsigned short cp_addr;
unsigned short reserved2;
unsigned short cp_data;
unsigned short reserved3;
unsigned short cp_ctrl;
};
#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
/* CPU version */
#define CCN_PRR 0xff000044
#define prr_mask(_val) ((_val >> 4) & 0xff)
#define PRR_SH7757_B0 0x10
#define PRR_SH7757_C0 0x11
#define is_sh7757_b0(_val) \
({ \
int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
__ret; \
})
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7757_H_ */
#
# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := sh7757lcr.o spi-boot.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
$(call cmd_link_o_target, $(COBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
This diff is collapsed.
This diff is collapsed.
/*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License. See the file "COPYING.LIB" in the main
* directory of this archive for more details.
*/
#include <common.h>
#define CONFIG_RAM_BOOT_PHYS 0x4ef80000
#if defined(CONFIG_SH7757_OFFSET_SPI)
#define CONFIG_SPI_ADDR 0x00010000
#else
#define CONFIG_SPI_ADDR 0x00000000
#endif
#define CONFIG_SPI_LENGTH 0x00030000
#define CONFIG_RAM_BOOT 0x8ef80000
#define SPIWDMADR 0xFE001018
#define SPIWDMCNTR 0xFE001020
#define SPIDMCOR 0xFE001028
#define SPIDMINTSR 0xFE001188
#define SPIDMINTMR 0xFE001190
#define SPIDMINTSR_DMEND 0x00000004
#define TBR 0xFE002000
#define RBR 0xFE002000
#define CR1 0xFE002008
#define CR2 0xFE002010
#define CR3 0xFE002018
#define CR4 0xFE002020
/* CR1 */
#define SPI_TBE 0x80
#define SPI_TBF 0x40
#define SPI_RBE 0x20
#define SPI_RBF 0x10
#define SPI_PFONRD 0x08
#define SPI_SSDB 0x04
#define SPI_SSD 0x02
#define SPI_SSA 0x01
/* CR2 */
#define SPI_RSTF 0x80
#define SPI_LOOPBK 0x40
#define SPI_CPOL 0x20
#define SPI_CPHA 0x10
#define SPI_L1M0 0x08
/* CR4 */
#define SPI_TBEI 0x80
#define SPI_TBFI 0x40
#define SPI_RBEI 0x20
#define SPI_RBFI 0x10
#define SPI_SSS 0x01
#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
#define spi_read(addr) (*(volatile unsigned long *)(addr))
/* M25P80 */
#define M25_READ 0x03
#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
static void __uses_spiboot2 spi_reset(void)
{
spi_write(0xfe, CR1);
spi_write(0, SPIDMCOR);
spi_write(0x00, CR1);
spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
}
static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
unsigned long len)
{
spi_write(M25_READ, TBR);
spi_write((addr >> 16) & 0xFF, TBR);
spi_write((addr >> 8) & 0xFF, TBR);
spi_write(addr & 0xFF, TBR);
spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
spi_write((unsigned long)buf, SPIWDMADR);
spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
spi_write(1, SPIDMCOR);
spi_write(0xff, CR3);
spi_write(spi_read(CR1) | SPI_SSDB, CR1);
spi_write(spi_read(CR1) | SPI_SSA, CR1);
while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
;
}
void __uses_spiboot2 spiboot_main(void)
{
void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
spi_reset();
spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
CONFIG_SPI_LENGTH);
_start();
}
/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2011
* Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
* entry and reloct_dst will be provided via ldflags
*/
. = .;
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
arch/sh/cpu/sh4/start.o (.text)
*(.spiboot1.text)
*(.spiboot2.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
common/env_embedded.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss (NOLOAD) :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}
......@@ -745,6 +745,7 @@ ms7750se sh sh4 ms7750se -
ap325rxa sh sh4 ap325rxa renesas -
r2dplus sh sh4 r2dplus renesas -
r7780mp sh sh4 r7780mp renesas -
sh7757lcr sh sh4 sh7757lcr renesas -
sh7763rdp sh sh4 sh7763rdp renesas -
sh7785lcr sh sh4 sh7785lcr renesas -
sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
......
========================================
Renesas R0P7757LC0030RL board
========================================
This board specification:
=========================
The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
- SH7757 (SH-4A)
- DDR3-SDRAM 256MB (with ECC)
- SPI ROM 8MB
- 2D Graphic controller
- Ethernet controller
configuration for This board:
=============================
You can select the configuration as follows:
- make sh7785lcr_config
This board specific command:
============================
This board has the following its specific command:
- sh_g200
- write_mac
1. sh_g200
If we run this command, SH4 can control the G200.
The default setting is that SH4 cannot control the G200.
2. write_mac
You can write MAC address to SPI ROM.
Usage 1) Write MAC address
write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
For example)
=> write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
*) We have to input the command as a single line
(without carriage return)
*) We have to reset after input the command.
Usage 2) Show current data
write_mac
For example)
=> write_mac
ETHERC ch0 = 00:00:87:6c:21:80
ETHERC ch1 = 00:00:87:6c:21:81
GETHERC ch0 = 00:00:87:6c:21:82
GETHERC ch1 = 00:00:87:6c:21:83
/*
* Configuation settings for the sh7757lcr board
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SH7757LCR_H
#define __SH7757LCR_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4A 1
#define CONFIG_SH_32BIT 1
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SF
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_CMD_LOADS
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7757LCR_SDRAM_BASE (0x80000000)
#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE 512
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
224 * 1024 * 1024)
#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 + 16) * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_SYS_NO_FLASH
/* Ether */
#define CONFIG_NET_MULTI 1
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
#define SH7757LCR_ETHERNET_MAC_SIZE 17
#define SH7757LCR_ETHERNET_NUM_CH 2
#define BOARD_LATE_INIT 1
/* Gigabit Ether */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
#define SH7757LCR_GRA_OFFSET 0x1f000000
#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
#define SH7757LCR_PCIEBRG_ADDR 0x00090000
#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netboot=bootp; bootm\0"
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 48000000
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __SH7757LCR_H */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment