Commit 8ed96046 authored by wdenk's avatar wdenk

* Patches by Richard Woodruff, 01 Oct 2004:

  add support for the TI OMAP2420 processor and its H4 reference
  board

* Patch by Christian Pellegrin, 24 Sep 2004:
  Added support for NE2000 compatible (DP8390, DP83902) NICs.
parent ff36fd85
......@@ -2,6 +2,13 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patches by Richard Woodruff, 01 Oct 2004:
add support for the TI OMAP2420 processor and its H4 reference
board
* Patch by Christian Pellegrin, 24 Sep 2004:
Added support for NE2000 compatible (DP8390, DP83902) NICs.
* Patch by Leif Lindholm, 23 Sep 2004:
add support for the AMD db1550 board
......
......@@ -382,6 +382,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
David Mller <d.mueller@elsoft.ch>
smdk2410 ARM920T
......
......@@ -157,6 +157,11 @@ LIST_ARM9=" \
versatile \
"
#########################################################################
## ARM11 Systems
#########################################################################
LIST_ARM11="omap2420h4"
#########################################################################
## Xscale Systems
#########################################################################
......@@ -170,7 +175,11 @@ LIST_pxa=" \
LIST_ixp="ixdp425"
LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"
LIST_arm=" \
${LIST_SA} \
${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11} \
${LIST_pxa} ${LIST_ixp} \
"
#########################################################################
## MIPS Systems
......@@ -238,7 +247,7 @@ for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|pxa|ixp| \
arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
microblaze| \
mips| \
nios|nios2| \
......
......@@ -1403,6 +1403,12 @@ xm250_config : unconfig
xsengine_config : unconfig
@./mkconfig $(@:_config=) arm pxa xsengine
#########################################################################
## ARM1136 Systems
#########################################################################
omap2420h4_config : unconfig
@./mkconfig $(@:_config=) arm arm1136 omap2420h4
#========================================================================
# i386
#========================================================================
......
......@@ -130,6 +130,7 @@ Directory Hierarchy:
- s3c24x0 Files specific to Samsung S3C24X0 CPUs
- arm925t Files specific to ARM 925 CPUs
- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
- at91rm9200 Files specific to Atmel AT91RM9200 CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
......@@ -301,13 +302,13 @@ The following options need to be configured:
ARM based boards:
-----------------
CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK,
CONFIG_OSK_OMAP5912, CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
CONFIG_VCMA9
CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110,
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK,
CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON,
CONFIG_P2_OMAP730, CONFIG_SMDK2400, CONFIG_SMDK2410,
CONFIG_TRAB, CONFIG_VCMA9
MicroBlaze based boards:
------------------------
......@@ -2177,7 +2178,7 @@ configurations; the following names are supported:
FADS850SAR_config omap1610h2_config TQM850L_config
FADS860T_config omap1610inn_config TQM855L_config
FPS850L_config omap5912osk_config TQM860L_config
WALNUT405_config
omap2420h4_config WALNUT405_config
Yukon8220_config
ZPC1900_config
......
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := omap2420h4.o flash.o mem.o sys_info.o
SOBJS := platform.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
#
# (C) Copyright 2004
# Texas Instruments, <www.ti.com>
#
# TI H4 board with OMAP2420 (ARM1136) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1) ES2 will be configurable
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
# CONFIG_PARTIAL_SRAM must be defined to use this.
TEXT_BASE = 0x80e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
# Comment out //CONFIG_PARTIAL_SRAM for this one.
#
#TEXT_BASE = 0x40280000
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/*
* Board specific setup info
*
* (C) Copyright 2004
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
#ifdef CONFIG_PARTIAL_SRAM
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
* R1 = SRAM destination address.
*************************************************************************/
.global cpy_clk_code
cpy_clk_code:
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
mov r1, r1 /* r1 <- dest address (passed in) */
add r2, r2, r0 /* r2 <- source end address */
next2:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
bne next2
mov pc, lr /* back to caller */
/* ****************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
* -executed from SRAM.
* R0 = PRCM_CLKCFG_CTRL - addr of valid reg
* R1 = CM_CLKEN_PLL - addr dpll ctlr reg
* R2 = dpll value
* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
******************************************************************************/
.global go_to_speed
go_to_speed:
sub sp, sp, #0x4 /* get some stack space */
str r4, [sp] /* save r4's value */
/* move into fast relock bypass */
ldr r8, pll_ctl_add
mov r4, #0x2
str r4, [r8]
ldr r4, pll_stat
block:
ldr r8, [r4] /* wait for bypass to take effect */
and r8, r8, #0x3
cmp r8, #0x1
bne block
/* set new dpll dividers _after_ in bypass */
ldr r4, pll_div_add
ldr r8, pll_div_val
str r8, [r4]
/* now prepare GPMC (flash) for new dpll speed */
/* flash needs to be stable when we jump back to it */
ldr r4, cfg3_0_addr
ldr r8, cfg3_0_val
str r8, [r4]
ldr r4, cfg4_0_addr
ldr r8, cfg4_0_val
str r8, [r4]
ldr r4, cfg1_0_addr
ldr r8, [r4]
orr r8, r8, #0x3 /* up gpmc divider */
str r8, [r4]
/* setup to 2x loop though code. The first loop pre-loads the
* icache, the 2nd commits the prcm config, and locks the dpll
*/
mov r4, #0x1000 /* spin spin spin */
mov r8, #0x4 /* first pass condition & set registers */
cmp r8, #0x4
2:
ldrne r8, [r3] /* DPLL lock check */
and r8, r8, #0x7
cmp r8, #0x2
beq 4f
3:
subeq r8, r8, #0x1
streq r8, [r0] /* commit dividers (2nd time) */
nop
lloop1:
sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
nop
cmp r4, #0x0
bne lloop1
mov r4, #0x40000
cmp r8, #0x1
nop
streq r2, [r1] /* lock dpll (2nd time) */
nop
lloop2:
sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
nop
cmp r4, #0x0
bne lloop2
mov r4, #0x40000
cmp r8, #0x1
nop
ldreq r8, [r3] /* get lock condition for dpll */
cmp r8, #0x4 /* first time though? */
bne 2b
moveq r8, #0x2 /* set to dpll check condition. */
beq 3b /* if condition not true branch */
4:
ldr r4, [sp]
add sp, sp, #0x4 /* return stack space */
mov pc, lr /* back to caller, locked */
_go_to_speed: .word go_to_speed
/* these constants need to be close for PIC code */
cfg3_0_addr:
.word GPMC_CONFIG3_0
cfg3_0_val:
.word H4_24XX_GPMC_CONFIG3_0
cfg4_0_addr:
.word GPMC_CONFIG4_0
cfg4_0_val:
.word H4_24XX_GPMC_CONFIG4_0
cfg1_0_addr:
.word GPMC_CONFIG1_0
pll_ctl_add:
.word CM_CLKEN_PLL
pll_stat:
.word CM_IDLEST_CKGEN
pll_div_add:
.word CM_CLKSEL1_PLL
pll_div_val:
.word DPLL_VAL /* DPLL setting (300MHz default) */
#endif
.globl platformsetup
platformsetup:
mov r3, r0 /* save skip information */
#ifdef CONFIG_APTIX
ldr r0, REG_SDRC_MCFG_0
ldr r1, VAL_SDRC_MCFG_0
str r1, [r0]
ldr r0, REG_SDRC_MR_0
ldr r1, VAL_SDRC_MR_0
str r1, [r0]
/* a ddr needs emr1 set here */
ldr r0, REG_SDRC_SHARING
ldr r1, VAL_SDRC_SHARING
str r1, [r0]
ldr r0, REG_SDRC_RFR_CTRL_0
ldr r1, VAL_SDRC_RFR_CTRL_0
str r1, [r0]
/* little delay after init */
mov r2, #0x1800
1:
subs r2, r2, #0x1
bne 1b
#endif
#ifdef CONFIG_PARTIAL_SRAM
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
mov r0, r3 /* pass skip info to s_init */
bl s_init /* go setup pll,mux,memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
#endif
/* map interrupt controller */
ldr r0, VAL_INTH_SETUP
mcr p15, 0, r0, c15, c2, 4
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
REG_CONTROL_STATUS:
.word CONTROL_STATUS
VAL_INTH_SETUP:
.word PERIFERAL_PORT_BASE
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK
#ifdef CONFIG_APTIX
REG_SDRC_SHARING:
.word SDRC_SHARING
REG_SDRC_MCFG_0:
.word SDRC_MCFG_0
REG_SDRC_MR_0:
.word SDRC_MR_0
REG_SDRC_RFR_CTRL_0:
.word SDRC_RFR_CTRL
VAL_SDRC_SHARING:
.word VAL_H4_SDRC_SHARING
VAL_SDRC_MCFG_0:
.word VAL_H4_SDRC_MCFG_0
VAL_SDRC_MR_0:
.word VAL_H4_SDRC_MR_0
VAL_SDRC_RFR_CTRL_0:
.word VAL_H4_SDRC_RFR_CTRL_0
#endif
/*
* (C) Copyright 2004
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <i2c.h>
/**************************************************************************
* get_cpu_type() - low level get cpu type
* - no C globals yet.
* - just looking to say if this is a 2422 or 2420 or ...
* - to start with we will look at switch settings..
* - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
* (mux for 2420, non-mux for 2422).
***************************************************************************/
u32 get_cpu_type(void)
{
u32 v;
v = __raw_readl(TAP_IDCODE_REG);
v &= CPU_24XX_ID_MASK;
if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */
if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
return(CPU_2420);
else
return(CPU_2422);
} else
return(CPU_2420); /* don't know, say 2420 */
}
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
u32 get_cpu_rev(void)
{
u32 v;
v = __raw_readl(TAP_IDCODE_REG);
v = v >> 28;
return(v+1); /* currently 2422 and 2420 match up */
}
/***********************************************************
* get_mem_type() - identify type of mDDR part used.
* 2422 uses stacked DDR, 2 parts CS0/CS1.
* 2420 may have 1 or 2, no good way to know...only init 1...
* when eeprom data is up we can select 1 more.
*************************************************************/
u32 get_mem_type(void)
{
if (get_cpu_type() == CPU_2422)
return(DDR_STACKED);
if (get_board_type() == BOARD_H4_MENELAUS)
return(DDR_COMBO);
else
return(DDR_DISCRETE);
}
/***********************************************************************
* get_board_type() - get board type based on current production stats.
* --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
* when they are available we can get info from there. This should
* be correct of all known boards up until today.
************************************************************************/
u32 get_board_type(void)
{
if (i2c_probe(I2C_MENELAUS) == 0)
return(BOARD_H4_MENELAUS);
else
return(BOARD_H4_SDP);
}
/******************************************************************
* get_sysboot_value() - get init word settings (dip switch on h4)
******************************************************************/
u32 get_sysboot_value(void)
{
return(0x00000FFF & __raw_readl(CONTROL_STATUS));
}
/***************************************************************************
* get_gpmc0_base() - Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
* mis-leading compared to the TRM. For the most general case the mask
* needs to be also taken into account this does work in practice.
* - for u-boot we currently map:
* -- 0 to nothing,
* -- 4 to flash
* -- 8 to enent
* -- c to wifi
****************************************************************************/
u32 get_gpmc0_base(void)
{
u32 b;
b = __raw_readl(GPMC_CONFIG7_0);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return(b);
}
/*****************************************************************
* is_gpmc_muxed() - tells if address/data lines are multiplexed
*****************************************************************/
u32 is_gpmc_muxed(void)
{
u32 mux;
mux = get_sysboot_value();
if (mux & BIT1) /* if mux'ed */
return(GPMC_MUXED);
else
return(GPMC_NONMUXED);
}
/************************************************************************
* get_gpmc0_type() - read sysboot lines to see type of memory attached
************************************************************************/
u32 get_gpmc0_type(void)
{
u32 type;
type = get_sysboot_value();
if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
return(TYPE_NAND);
else
return(TYPE_NOR);
}
/*******************************************************************
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
*******************************************************************/
u32 get_gpmc0_width(void)
{
u32 width;
width = get_sysboot_value();
if ((width & 0xF) == (BIT3|BIT2))
return(WIDTH_8BIT);
else
return(WIDTH_16BIT);
}
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.
*********************************************************************/
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
{
u32 i = 0, val;
do {
++i;
val = __raw_readl(read_addr) & read_bit_mask;
if (val == match_value)
return(1);
if (i==bound)
return(0);
} while (1);
}
/*********************************************************************
* display_board_info() - print banner with board info.
*********************************************************************/
void display_board_info(u32 btype)
{
char cpu_2420[] = "2420";
char cpu_2422[] = "2422";
char db_men[] = "Menelaus";
char db_ip[]= "IP";
char *cpu_s, *db_s;
u32 cpu = get_cpu_type();
if(cpu == CPU_2420)
cpu_s = cpu_2420;
else
cpu_s = cpu_2422;
if(btype == BOARD_H4_MENELAUS)
db_s = db_men;
else
db_s = db_ip;
printf("TI H4 SDP Base Board with OMAP%s %s Daughter Board\n",cpu_s, db_s);
}
/*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm1136/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}
......@@ -99,11 +99,7 @@ uchar env_get_char_spec (int index)
int env_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
int crc1_ok =
(crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
int crc2_ok =
(crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
int crc1_ok = 0, crc2_ok = 0;
uchar flag1 = flash_addr->flags;
uchar flag2 = flash_addr_new->flags;
......@@ -112,6 +108,16 @@ int env_init(void)
ulong addr1 = (ulong)&(flash_addr->data);
ulong addr2 = (ulong)&(flash_addr_new->data);
#ifdef CONFIG_OMAP2420H4
int flash_probe(void);
if(flash_probe() == 0)
goto bad_flash;
#endif
crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
if (crc1_ok && ! crc2_ok) {
gd->env_addr = addr1;
gd->env_valid = 1;
......@@ -138,6 +144,9 @@ int env_init(void)
gd->env_valid = 2;
}
#ifdef CONFIG_OMAP2420H4
bad_flash:
#endif
return (0);
}
......@@ -252,15 +261,22 @@ Done:
int env_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_OMAP2420H4
int flash_probe(void);
if(flash_probe() == 0)
goto bad_flash;
#endif
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr = (ulong)&(env_ptr->data);
gd->env_valid = 1;
} else {
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 0;
return(0);
}
#ifdef CONFIG_OMAP2420H4
bad_flash:
#endif
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 0;
return (0);
}
......