Commit 8f695232 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tom Rini

memory: Move TI_AEMIF config to KCONFIG

Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.
Reported-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent 3bfc8152
......@@ -20,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_TI_AEMIF)
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
......@@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = {
.width = AEMIF_WIDTH_8,
},
};
#endif
int dram_init(void)
{
......@@ -42,7 +44,10 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#endif
if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
return 0;
......
......@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_TI_AEMIF=y
......@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_TI_AEMIF=y
......@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_TI_AEMIF=y
......@@ -30,6 +30,8 @@ source "drivers/input/Kconfig"
source "drivers/led/Kconfig"
source "drivers/memory/Kconfig"
source "drivers/misc/Kconfig"
source "drivers/mmc/Kconfig"
......
#
# Memory devices
#
menu "Memory Controller drivers"
config TI_AEMIF
tristate "Texas Instruments AEMIF driver"
depends on ARCH_KEYSTONE
help
This driver is for the AEMIF module available in Texas Instruments
SoCs. AEMIF stands for Asynchronous External Memory Interface and
is intended to provide a glue-less interface to a variety of
asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
of 256M bytes of any of these memories can be accessed at a given
time via four chip selects with 64M byte access per chip select.
endmenu
......@@ -145,8 +145,6 @@
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* I2C Configuration */
......
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