Commit 900fc692 authored by Hugo Grostabussiat's avatar Hugo Grostabussiat

imx8m: Add Purism Librem5 devkit board

This commit creates a new board for the Purism Librem5 devkit.

- The board code was copied from the emcraft/imx8m_som board, minus the
parts which were not relevant (other DDR configs).
- The Emcraft-specific preprocessor defines have been removed.
- A new librem5.h configuration file was created.
parent 5a34315e
...@@ -90,6 +90,12 @@ config TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM ...@@ -90,6 +90,12 @@ config TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
endchoice endchoice
config TARGET_PURISM_LIBREM5_DEVKIT
bool "Purism Librem5 devkit"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
config SYS_SOC config SYS_SOC
default "imx8m" default "imx8m"
...@@ -99,5 +105,6 @@ source "board/freescale/imx8mq_arm2/Kconfig" ...@@ -99,5 +105,6 @@ source "board/freescale/imx8mq_arm2/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mm_val/Kconfig" source "board/freescale/imx8mm_val/Kconfig"
source "board/emcraft/imx8m_som/Kconfig" source "board/emcraft/imx8m_som/Kconfig"
source "board/purism/librem5/Kconfig"
endif endif
../freescale/common
\ No newline at end of file
if TARGET_PURISM_LIBREM5_DEVKIT
config SYS_BOARD
default "librem5"
config SYS_VENDOR
default "purism"
config SYS_CONFIG_NAME
default "librem5"
config M4_LOAD_DDR_TRAINING
bool "Use the M4 to load the DDR training firmware"
endif
#
# Copyright 2016 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8m_som.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += ddr/lpddr4_3gb/ddr_init.o ddr/lpddr4_3gb/ddrphy_train.o \
ddr/lpddr4_3gb/helper.o
endif
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
enum fw_type {
FW_1D_IMAGE,
FW_2D_IMAGE,
};
void ddr_init(void);
void ddr_load_train_code(enum fw_type type);
void lpddr4_800M_cfg_phy(void);
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
}
static inline uint32_t reg32_read(unsigned long addr)
{
return readl(addr);
}
static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
{
writel(val, addr);
}
static inline void reg32setbit(unsigned long addr, u32 bit)
{
setbits_le32(addr, (1 << bit));
}
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Generated code from MX8M_DDR_tool
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr_memory_map.h>
#include <asm/arch/clock.h>
#include "ddr.h"
#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
#define ddr_printf(args...) printf(args)
#else
#define ddr_printf(args...)
#endif
#include "wait_ddrphy_training_complete.c"
#ifndef SRC_DDRC_RCR_ADDR
#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
#endif
#ifndef DDR_CSD1_BASE_ADDR
#define DDR_CSD1_BASE_ADDR 0x40000000
#endif
#define SILICON_TRAIN
void ddr_cfg_phy(void);
volatile unsigned int tmp, tmp_t, i;
void ddr_init(void)
{
/** Initialize DDR clock and DDRC registers **/
reg32_write(0x3038a088,0x7070000);
reg32_write(0x3038a084,0x4030000);
reg32_write(0x303a00ec,0xffff);
tmp=reg32_read(0x303a00f8);
tmp |= 0x20;
reg32_write(0x303a00f8,tmp);
reg32_write(0x30391000,0x8f000000);
reg32_write(0x30391004,0x8f000000);
reg32_write(0x30360068,0xece580);
tmp=reg32_read(0x30360060);
tmp &= ~0x80;
reg32_write(0x30360060,tmp);
tmp=reg32_read(0x30360060);
tmp |= 0x200;
reg32_write(0x30360060,tmp);
tmp=reg32_read(0x30360060);
tmp &= ~0x20;
reg32_write(0x30360060,tmp);
tmp=reg32_read(0x30360060);
tmp &= ~0x10;
reg32_write(0x30360060,tmp);
do{
tmp=reg32_read(0x30360060);
if(tmp&0x80000000) break;
}while(1);
reg32_write(0x30391000,0x8f000006);
reg32_write(0x3d400304,0x1);
reg32_write(0x3d400030,0x1);
reg32_write(0x3d400000,0xa3080020);
reg32_write(0x3d400028,0x0);
reg32_write(0x3d400020,0x203);
reg32_write(0x3d400024,0x186a000);
reg32_write(0x3d400064,0x6100e0);
reg32_write(0x3d4000d0,0xc003061c);
reg32_write(0x3d4000d4,0x9e0000);
reg32_write(0x3d4000dc,0xd4002d);
reg32_write(0x3d4000e0,0x310008);
reg32_write(0x3d4000e8,0x66004a);
reg32_write(0x3d4000ec,0x16004a);
reg32_write(0x3d400100,0x1a201b22);
reg32_write(0x3d400104,0x60633);
reg32_write(0x3d40010c,0xc0c000);
reg32_write(0x3d400110,0xf04080f);
reg32_write(0x3d400114,0x2040c0c);
reg32_write(0x3d400118,0x1010007);
reg32_write(0x3d40011c,0x401);
reg32_write(0x3d400130,0x20600);
reg32_write(0x3d400134,0xc100002);
reg32_write(0x3d400138,0xe6);
reg32_write(0x3d400144,0xa00050);
reg32_write(0x3d400180,0x3200018);
reg32_write(0x3d400184,0x28061a8);
reg32_write(0x3d400188,0x0);
reg32_write(0x3d400190,0x497820a);
reg32_write(0x3d400194,0x80303);
reg32_write(0x3d4001a0,0xe0400018);
reg32_write(0x3d4001a4,0xdf00e4);
reg32_write(0x3d4001a8,0x80000000);
reg32_write(0x3d4001b0,0x11);
reg32_write(0x3d4001b4,0x170a);
reg32_write(0x3d4001c0,0x1);
reg32_write(0x3d4001c4,0x1);
reg32_write(0x3d4000f4,0x639);
reg32_write(0x3d400108,0x70e1214);
reg32_write(0x3d400200,0x15);
reg32_write(0x3d40020c,0x0);
reg32_write(0x3d400210,0x1f1f);
reg32_write(0x3d400204,0x80808);
reg32_write(0x3d400214,0x7070707);
reg32_write(0x3d400218,0x48080707);
reg32_write(0x3d402020,0x1);
reg32_write(0x3d402024,0x518b00);
reg32_write(0x3d402050,0x20d040);
reg32_write(0x3d402064,0x14002f);
reg32_write(0x3d4020dc,0x940009);
reg32_write(0x3d4020e0,0x310000);
reg32_write(0x3d4020e8,0x66004a);
reg32_write(0x3d4020ec,0x16004a);
reg32_write(0x3d402100,0xb070508);
reg32_write(0x3d402104,0x3040b);
reg32_write(0x3d402108,0x305090c);
reg32_write(0x3d40210c,0x505000);
reg32_write(0x3d402110,0x4040204);
reg32_write(0x3d402114,0x2030303);
reg32_write(0x3d402118,0x1010004);
reg32_write(0x3d40211c,0x301);
reg32_write(0x3d402130,0x20300);
reg32_write(0x3d402134,0xa100002);
reg32_write(0x3d402138,0x31);
reg32_write(0x3d402144,0x220011);
reg32_write(0x3d402180,0xa70006);
reg32_write(0x3d402190,0x3858202);
reg32_write(0x3d402194,0x80303);
reg32_write(0x3d4021b4,0x502);
reg32_write(0x3d400244,0x0);
reg32_write(0x3d400250,0x29001505);
reg32_write(0x3d400254,0x2c);
reg32_write(0x3d40025c,0x5900575b);
reg32_write(0x3d400264,0x9);
reg32_write(0x3d40026c,0x2005574);
reg32_write(0x3d400300,0x16);
reg32_write(0x3d400304,0x0);
reg32_write(0x3d40030c,0x0);
reg32_write(0x3d400320,0x1);
reg32_write(0x3d40036c,0x11);
reg32_write(0x3d400400,0x111);
reg32_write(0x3d400404,0x10f3);
reg32_write(0x3d400408,0x72ff);
reg32_write(0x3d400490,0x1);
reg32_write(0x3d400494,0x1110d00);
reg32_write(0x3d400498,0x620790);
reg32_write(0x3d40049c,0x100001);
reg32_write(0x3d4004a0,0x41f);
reg32_write(0x30391000,0x8f000004);
reg32_write(0x30391000,0x8f000000);
reg32_write(0x3d400030,0xa8);
do{
tmp=reg32_read(0x3d400004);
if(tmp&0x223) break;
}while(1);
reg32_write(0x3d400320,0x0);
reg32_write(0x3d000000,0x1);
reg32_write(0x3d4001b0,0x10);
reg32_write(0x3c040280,0x0);
reg32_write(0x3c040284,0x1);
reg32_write(0x3c040288,0x2);
reg32_write(0x3c04028c,0x3);
reg32_write(0x3c040290,0x4);
reg32_write(0x3c040294,0x5);
reg32_write(0x3c040298,0x6);
reg32_write(0x3c04029c,0x7);
reg32_write(0x3c044280,0x0);
reg32_write(0x3c044284,0x1);
reg32_write(0x3c044288,0x2);
reg32_write(0x3c04428c,0x3);
reg32_write(0x3c044290,0x4);
reg32_write(0x3c044294,0x5);
reg32_write(0x3c044298,0x6);
reg32_write(0x3c04429c,0x7);
reg32_write(0x3c048280,0x0);
reg32_write(0x3c048284,0x1);
reg32_write(0x3c048288,0x2);
reg32_write(0x3c04828c,0x3);
reg32_write(0x3c048290,0x4);
reg32_write(0x3c048294,0x5);
reg32_write(0x3c048298,0x6);
reg32_write(0x3c04829c,0x7);
reg32_write(0x3c04c280,0x0);
reg32_write(0x3c04c284,0x1);
reg32_write(0x3c04c288,0x2);
reg32_write(0x3c04c28c,0x3);
reg32_write(0x3c04c290,0x4);
reg32_write(0x3c04c294,0x5);
reg32_write(0x3c04c298,0x6);
reg32_write(0x3c04c29c,0x7);
/* Configure DDR PHY's registers */
ddr_cfg_phy();
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
reg32_write(DDRC_SWCTL(0), 0x0000);
/*
* ------------------- 9 -------------------
* Set DFIMISC.dfi_init_start to 1
* -----------------------------------------
*/
reg32_write(DDRC_DFIMISC(0), 0x00000030);
reg32_write(DDRC_SWCTL(0), 0x0001);
/* wait DFISTAT.dfi_init_complete to 1 */
tmp_t = 0;
while(tmp_t==0){
tmp = reg32_read(DDRC_DFISTAT(0));
tmp_t = tmp & 0x01;
tmp = reg32_read(DDRC_MRSTAT(0));
}
reg32_write(DDRC_SWCTL(0), 0x0000);
/* clear DFIMISC.dfi_init_complete_en */
reg32_write(DDRC_DFIMISC(0), 0x00000010);
reg32_write(DDRC_DFIMISC(0), 0x00000011);
reg32_write(DDRC_PWRCTL(0), 0x00000088);
tmp = reg32_read(DDRC_CRCPARSTAT(0));
/*
* set SWCTL.sw_done to enable quasi-dynamic register
* programming outside reset.
*/
reg32_write(DDRC_SWCTL(0), 0x00000001);
/* wait SWSTAT.sw_done_ack to 1 */
while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
;
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
;
reg32_write(DDRC_PWRCTL(0), 0x00000088);
/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
tmp = reg32_read(DDRC_CRCPARSTAT(0));
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
/* enable DDR auto-refresh mode */
tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
reg32_write(DDRC_RFSHCTL3(0), tmp);
}
\ No newline at end of file
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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
static inline void poll_pmu_message_ready(void)
{
unsigned int reg;
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
} while (reg & 0x1);
}
static inline void ack_pmu_message_recieve(void)
{
unsigned int reg;
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
} while (!(reg & 0x1));
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
}
static inline unsigned int get_mail(void)
{
unsigned int reg;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
ack_pmu_message_recieve();
return reg;
}
static inline unsigned int get_stream_message(void)
{
unsigned int reg, reg2;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
reg2 = (reg2 << 16) | reg;
ack_pmu_message_recieve();
return reg2;
}
static inline void decode_major_message(unsigned int mail)
{
ddr_printf("[PMU Major message = 0x%08x]\n", mail);
}
static inline void decode_streaming_message(void)
{
unsigned int string_index, arg __maybe_unused;
int i = 0;
string_index = get_stream_message();
ddr_printf(" PMU String index = 0x%08x\n", string_index);
while (i < (string_index & 0xffff)){
arg = get_stream_message();
ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
i++;
}
ddr_printf("\n");
}
void wait_ddrphy_training_complete(void)
{
unsigned int mail;
while (1) {
mail = get_mail();
decode_major_message(mail);
if (mail == 0x08) {
decode_streaming_message();
} else if (mail == 0x07) {
/* Training PASS */
break;
} else if (mail == 0xff) {
printf("Training FAILED\n");
break;
}
}
}
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017 EmCraft Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <power/pmic.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <linux/usb/ch9.h>
DECLARE_GLOBAL_DATA_PTR;
#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#ifdef CONFIG_FSL_QSPI
static iomux_v3_cfg_t const qspi_pads[] = {
IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
};
int board_qspi_init(void)
{
imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
set_clk_qspi();
return 0;
}
#endif
static iomux_v3_cfg_t const uart_pads[] = {
#if defined(CONFIG_MXC_UART_BASE)
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
#if (CONFIG_MXC_UART_BASE == UART3_BASE_ADDR)
IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
#endif
#endif
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
/* TODO */
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 | MUX_PAD_CTRL(0x1F),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads));
gpio_request(FEC_RST_PAD, "fec1_rst");
gpio_direction_output(FEC_RST_PAD, 0);
udelay(500);
gpio_direction_output(FEC_RST_PAD, 1);
}
static int setup_fec(void)
{
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(IOMUXC_GPR1,
BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHz);
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
#define USB_PHY_CTRL0 0xF0040
#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
#define USB_PHY_CTRL1 0xF0044
#define USB_PHY_CTRL1_RESET BIT(0)
#define USB_PHY_CTRL1_COMMONONN BIT(1)
#define USB_PHY_CTRL1_ATERESET BIT(3)
#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
#define USB_PHY_CTRL2 0xF0048
#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_SUPER,
.base = USB1_BASE_ADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.power_down_scale = 2,
};
static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
{
u32 RegData;
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
USB_PHY_CTRL1_COMMONONN);
RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
writel(RegData, dwc3->base + USB_PHY_CTRL1);
RegData = readl(dwc3->base + USB_PHY_CTRL0);
RegData |= USB_PHY_CTRL0_REF_SSP_EN;
writel(RegData, dwc3->base + USB_PHY_CTRL0);
RegData = readl(dwc3->base + USB_PHY_CTRL2);
RegData |= USB_PHY_CTRL2_TXENABLEN0;
writel(RegData, dwc3->base + USB_PHY_CTRL2);
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
writel(RegData, dwc3->base + USB_PHY_CTRL1);
}
#endif
int usb_gadget_handle_interrupts(void)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}
#ifdef CONFIG_USB_TCPC
struct tcpc_port port;
struct tcpc_port_config port_config = {
.i2c_bus = 0,
.addr = 0x50,
.port_type = TYPEC_PORT_UFP,
.max_snk_mv = 20000,
.max_snk_ma = 3000,
.max_snk_mw = 15000,
.op_snk_mv = 9000,
};
#define USB_TYPEC_SEL IMX_GPIO_NR(3, 15)
static iomux_v3_cfg_t ss_mux_gpio[] = {
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
void ss_mux_select(enum typec_cc_polarity pol)
{
if (pol == TYPEC_POLARITY_CC1)
gpio_direction_output(USB_TYPEC_SEL, 1);
else
gpio_direction_output(USB_TYPEC_SEL, 0);
}
static int setup_typec(void)
{
int ret;
imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
gpio_request(USB_TYPEC_SEL, "typec_sel");
ret = tcpc_init(&port, port_config, &ss_mux_select);
if (ret) {
printf("%s: tcpc init failed, err=%d\n",
__func__, ret);
}
return ret;
}
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
imx8m_usb_power(index, true);
if (index == 0 && init == USB_INIT_DEVICE) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_ufp_mode(&port);
#endif
dwc3_nxp_usb_phy_init(&dwc3_device_data);
return dwc3_uboot_init(&dwc3_device_data);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_dfp_mode(&port);
#endif
return ret;
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 0 && init == USB_INIT_DEVICE) {
dwc3_uboot_exit(index);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_disable_src_vbus(&port);
#endif
}
imx8m_usb_power(index, false);
return ret;
}
#endif
int board_init(void)
{
board_qspi_init();
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#ifdef CONFIG_USB_TCPC
setup_typec();
#endif
return 0;
return 0;
}