Commit 9122109a authored by Peter Griffin's avatar Peter Griffin Committed by Tom Rini

ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.

Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent 11b9a4d8
/*
* dts file for Hisilicon HiKey Development Board
*
* Copyright (C) 2015, Hisilicon Ltd.
*
*/
/dts-v1/;
/*Reserved 1MB memory for MCU*/
/memreserve/ 0x05e00000 0x00100000;
#include "hi6220.dtsi"
/ {
model = "HiKey Development Board";
compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
aliases {
serial0 = &uart0; /* On board UART0 */
serial1 = &uart1; /* BT UART */
serial2 = &uart2; /* LS Expansion UART0 */
serial3 = &uart3; /* LS Expansion UART1 */
};
chosen {
stdout-path = "serial3:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&uart2 {
label = "LS-UART0";
};
&uart3 {
label = "LS-UART1";
};
/*
* dts file for Hisilicon Hi6220 SoC
*
* Copyright (C) 2015, Hisilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi6220-clock.h>
/ {
compatible = "hisilicon,hi6220";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
};
};
gic: interrupt-controller@f6801000 {
compatible = "arm,gic-400";
reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
<0x0 0xf6802000 0 0x2000>, /* GICC */
<0x0 0xf6804000 0 0x2000>, /* GICH */
<0x0 0xf6806000 0 0x2000>; /* GICV */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
};
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
media_ctrl: media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
};
pm_ctrl: pm_ctrl@f7032000 {
compatible = "hisilicon,hi6220-pmctrl", "syscon";
reg = <0x0 0xf7032000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: uart@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ao_ctrl HI6220_UART0_PCLK>,
<&ao_ctrl HI6220_UART0_PCLK>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@f7111000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7111000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART1_PCLK>,
<&sys_ctrl HI6220_UART1_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: uart@f7112000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7112000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART2_PCLK>,
<&sys_ctrl HI6220_UART2_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: uart@f7113000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7113000 0x0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART3_PCLK>,
<&sys_ctrl HI6220_UART3_PCLK>;
clock-names = "uartclk", "apb_pclk";
};
uart4: uart@f7114000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7114000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART4_PCLK>,
<&sys_ctrl HI6220_UART4_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};
/*
* Copyright (c) 2015 Hisilicon Limited.
*
* Author: Bintian Wang <bintian.wang@huawei.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_CLOCK_HI6220_H
#define __DT_BINDINGS_CLOCK_HI6220_H
/* clk in Hi6220 AO (always on) controller */
#define HI6220_NONE_CLOCK 0
/* fixed rate clocks */
#define HI6220_REF32K 1
#define HI6220_CLK_TCXO 2
#define HI6220_MMC1_PAD 3
#define HI6220_MMC2_PAD 4
#define HI6220_MMC0_PAD 5
#define HI6220_PLL_BBP 6
#define HI6220_PLL_GPU 7
#define HI6220_PLL1_DDR 8
#define HI6220_PLL_SYS 9
#define HI6220_PLL_SYS_MEDIA 10
#define HI6220_DDR_SRC 11
#define HI6220_PLL_MEDIA 12
#define HI6220_PLL_DDR 13
/* fixed factor clocks */
#define HI6220_300M 14
#define HI6220_150M 15
#define HI6220_PICOPHY_SRC 16
#define HI6220_MMC0_SRC_SEL 17
#define HI6220_MMC1_SRC_SEL 18
#define HI6220_MMC2_SRC_SEL 19
#define HI6220_VPU_CODEC 20
#define HI6220_MMC0_SMP 21
#define HI6220_MMC1_SMP 22
#define HI6220_MMC2_SMP 23
/* gate clocks */
#define HI6220_WDT0_PCLK 24
#define HI6220_WDT1_PCLK 25
#define HI6220_WDT2_PCLK 26
#define HI6220_TIMER0_PCLK 27
#define HI6220_TIMER1_PCLK 28
#define HI6220_TIMER2_PCLK 29
#define HI6220_TIMER3_PCLK 30
#define HI6220_TIMER4_PCLK 31
#define HI6220_TIMER5_PCLK 32
#define HI6220_TIMER6_PCLK 33
#define HI6220_TIMER7_PCLK 34
#define HI6220_TIMER8_PCLK 35
#define HI6220_UART0_PCLK 36
#define HI6220_AO_NR_CLKS 37
/* clk in Hi6220 systrl */
/* gate clock */
#define HI6220_MMC0_CLK 1
#define HI6220_MMC0_CIUCLK 2
#define HI6220_MMC1_CLK 3
#define HI6220_MMC1_CIUCLK 4
#define HI6220_MMC2_CLK 5
#define HI6220_MMC2_CIUCLK 6
#define HI6220_USBOTG_HCLK 7
#define HI6220_CLK_PICOPHY 8
#define HI6220_HIFI 9
#define HI6220_DACODEC_PCLK 10
#define HI6220_EDMAC_ACLK 11
#define HI6220_CS_ATB 12
#define HI6220_I2C0_CLK 13
#define HI6220_I2C1_CLK 14
#define HI6220_I2C2_CLK 15
#define HI6220_I2C3_CLK 16
#define HI6220_UART1_PCLK 17
#define HI6220_UART2_PCLK 18
#define HI6220_UART3_PCLK 19
#define HI6220_UART4_PCLK 20
#define HI6220_SPI_CLK 21
#define HI6220_TSENSOR_CLK 22
#define HI6220_MMU_CLK 23
#define HI6220_HIFI_SEL 24
#define HI6220_MMC0_SYSPLL 25
#define HI6220_MMC1_SYSPLL 26
#define HI6220_MMC2_SYSPLL 27
#define HI6220_MMC0_SEL 28
#define HI6220_MMC1_SEL 29
#define HI6220_BBPPLL_SEL 30
#define HI6220_MEDIA_PLL_SRC 31
#define HI6220_MMC2_SEL 32
#define HI6220_CS_ATB_SYSPLL 33
/* mux clocks */
#define HI6220_MMC0_SRC 34
#define HI6220_MMC0_SMP_IN 35
#define HI6220_MMC1_SRC 36
#define HI6220_MMC1_SMP_IN 37
#define HI6220_MMC2_SRC 38
#define HI6220_MMC2_SMP_IN 39
#define HI6220_HIFI_SRC 40
#define HI6220_UART1_SRC 41
#define HI6220_UART2_SRC 42
#define HI6220_UART3_SRC 43
#define HI6220_UART4_SRC 44
#define HI6220_MMC0_MUX0 45
#define HI6220_MMC1_MUX0 46
#define HI6220_MMC2_MUX0 47
#define HI6220_MMC0_MUX1 48
#define HI6220_MMC1_MUX1 49
#define HI6220_MMC2_MUX1 50
/* divider clocks */
#define HI6220_CLK_BUS 51
#define HI6220_MMC0_DIV 52
#define HI6220_MMC1_DIV 53
#define HI6220_MMC2_DIV 54
#define HI6220_HIFI_DIV 55
#define HI6220_BBPPLL0_DIV 56
#define HI6220_CS_DAPB 57
#define HI6220_CS_ATB_DIV 58
#define HI6220_SYS_NR_CLKS 59
/* clk in Hi6220 media controller */
/* gate clocks */
#define HI6220_DSI_PCLK 1
#define HI6220_G3D_PCLK 2
#define HI6220_ACLK_CODEC_VPU 3
#define HI6220_ISP_SCLK 4
#define HI6220_ADE_CORE 5
#define HI6220_MED_MMU 6
#define HI6220_CFG_CSI4PHY 7
#define HI6220_CFG_CSI2PHY 8
#define HI6220_ISP_SCLK_GATE 9
#define HI6220_ISP_SCLK_GATE1 10
#define HI6220_ADE_CORE_GATE 11
#define HI6220_CODEC_VPU_GATE 12
#define HI6220_MED_SYSPLL 13
/* mux clocks */
#define HI6220_1440_1200 14
#define HI6220_1000_1200 15
#define HI6220_1000_1440 16
/* divider clocks */
#define HI6220_CODEC_JPEG 17
#define HI6220_ISP_SCLK_SRC 18
#define HI6220_ISP_SCLK1 19
#define HI6220_ADE_CORE_SRC 20
#define HI6220_ADE_PIX_SRC 21
#define HI6220_G3D_CLK 22
#define HI6220_CODEC_VPU_SRC 23
#define HI6220_MEDIA_NR_CLKS 24
/* clk in Hi6220 power controller */
/* gate clocks */
#define HI6220_PLL_GPU_GATE 1
#define HI6220_PLL1_DDR_GATE 2
#define HI6220_PLL_DDR_GATE 3
#define HI6220_PLL_MEDIA_GATE 4
#define HI6220_PLL0_BBP_GATE 5
/* divider clocks */
#define HI6220_DDRC_SRC 6
#define HI6220_DDRC_AXI1 7
#define HI6220_POWER_NR_CLKS 8
#endif
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