Commit 92a190aa authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Tom Rini

net/designware - switch driver to phylib usage

With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
parent 27ee59af
......@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
if (CONFIG_DW_PORTS & 1) {
static const unsigned short pins[] = P_RMII0;
if (!peripheral_request_list(pins, "emac0"))
ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
ret += designware_initialize(EMAC0_MACCFG, 0);
}
if (CONFIG_DW_PORTS & 2) {
static const unsigned short pins[] = P_RMII1;
if (!peripheral_request_list(pins, "emac1"))
ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
ret += designware_initialize(EMAC1_MACCFG, 0);
}
return ret;
......
......@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
return ret;
......
......@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
#if defined(CONFIG_MACB)
......
......@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
#if defined(CONFIG_MACB)
......
......@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DW_AUTONEG)
interface = PHY_INTERFACE_MODE_GMII;
#endif
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
return ret;
......
......@@ -67,31 +67,32 @@ void board_nand_init(void)
fsmc_nand_init(nand);
}
int designware_board_phy_init(struct eth_device *dev, int phy_addr,
int (*mii_write)(struct eth_device *, u8, u8, u16),
int dw_reset_phy(struct eth_device *))
int board_phy_config(struct phy_device *phydev)
{
/* Extended PHY control 1, select GMII */
mii_write(dev, phy_addr, 23, 0x0020);
phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
/* Software reset necessary after GMII mode selction */
dw_reset_phy(dev);
phy_reset(phydev);
/* Enable extended page register access */
mii_write(dev, phy_addr, 31, 0x0001);
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
/* 17e: Enhanced LED behavior, needs to be written twice */
mii_write(dev, phy_addr, 17, 0x09ff);
mii_write(dev, phy_addr, 17, 0x09ff);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
/* 16e: Enhanced LED method select */
mii_write(dev, phy_addr, 16, 0xe0ea);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
/* Disable extended page register access */
mii_write(dev, phy_addr, 31, 0x0000);
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
/* Enable clock output pin */
mii_write(dev, phy_addr, 18, 0x0049);
phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
......@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
{
int ret = 0;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
if (designware_initialize(CONFIG_SPEAR_ETHBASE,
PHY_INTERFACE_MODE_GMII) >= 0)
ret++;
......
This driver supports Designware Ethernet Controller provided by Synopsis.
The driver is enabled by CONFIG_DESIGNWARE_ETH.
The driver has been developed and tested on SPEAr platforms. By default, the
MDIO interface works at 100/Full. #defining the below options in board
configuration file changes this behavior.
Call an subroutine from respective board/.../board.c
designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
The various options suported by the driver are
1. CONFIG_DW_ALTDESCRIPTOR
Define this to use the Alternate/Enhanced Descriptor configurations.
1. CONFIG_DW_AUTONEG
Define this to autonegotiate with the host before proceeding with mac
level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
and CONFIG_DW_DUPLEXHALF.
2. CONFIG_DW_SPEED10M
Define this to change the default behavior from 100Mbps to 10Mbps.
3. CONFIG_DW_DUPLEXHALF
Define this to change the default behavior from Full Duplex to Half.
4. CONFIG_DW_SEARCH_PHY
Define this to search the phy address. This would overwrite the value
passed as 3rd arg from designware_initialize routine.
This diff is collapsed.
......@@ -16,8 +16,6 @@
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
......@@ -217,14 +215,9 @@ struct dmamacdescr {
#endif
struct dw_eth_dev {
u32 address;
u32 interface;
u32 speed;
u32 duplex;
u32 tx_currdescnum;
u32 rx_currdescnum;
u32 phy_configured;
u32 link_printed;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
......@@ -236,15 +229,8 @@ struct dw_eth_dev {
struct eth_dma_regs *dma_regs_p;
struct eth_device *dev;
struct phy_device *phydev;
struct mii_dev *bus;
};
/* Speed specific definitions */
#define SPEED_10M 1
#define SPEED_100M 2
#define SPEED_1000M 3
/* Duplex mode specific definitions */
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
#endif
......@@ -72,12 +72,13 @@
#define CONFIG_NET_MULTI
#define CONFIG_HOSTNAME "bf609-ezkit"
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_PHY_ADDR 1
#define CONFIG_DW_PORTS 1
#define CONFIG_DW_AUTONEG
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_BFIN_TWI_I2C
......
......@@ -17,11 +17,9 @@
/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_SEARCH_PHY
#define CONFIG_DW0_PHY 1
#define CONFIG_NET_MULTI
#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* USBD driver configuration */
......
......@@ -37,6 +37,9 @@
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_BASE 0xD2000000
/* Ethernet PHY configuration */
#define CONFIG_PHY_NATSEMI
/* Environment Settings */
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
......
......@@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
int designware_initialize(ulong base_addr, u32 interface);
int dm9000_initialize(bd_t *bis);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
......
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