Commit 93e14596 authored by Wolfgang Denk's avatar Wolfgang Denk Committed by Tom Rini

Coding Style cleanup: replace leading SPACEs by TABs

Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: default avatarTom Rini <trini@ti.com>
parent 3765b3e7
......@@ -38,8 +38,8 @@ usage()
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILE cross-compiler toolchain prefix (default: "")
CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
architecture "ARCH". Substitute "ARCH" for any
supported architecture (default: "")
architecture "ARCH". Substitute "ARCH" for any
supported architecture (default: "")
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIR output build directory (default: ./)
BUILD_NBUILDS number of parallel targets (default: 1)
......
......@@ -944,10 +944,10 @@ The following options need to be configured:
- Regular expression support:
CONFIG_REGEX
If this variable is defined, U-Boot is linked against
the SLRE (Super Light Regular Expression) library,
which adds regex support to some commands, as for
example "env grep" and "setexpr".
If this variable is defined, U-Boot is linked against
the SLRE (Super Light Regular Expression) library,
which adds regex support to some commands, as for
example "env grep" and "setexpr".
- Device tree:
CONFIG_OF_CONTROL
......@@ -1096,8 +1096,8 @@ The following options need to be configured:
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
- NETWORK Support (PCI):
CONFIG_E1000
......@@ -1987,7 +1987,7 @@ CBFS (Coreboot Filesystem) support
offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
bus.
- If your board supports a second fsl i2c bus, define
- If your board supports a second fsl i2c bus, define
CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
CONFIG_SYS_FSL_I2C2_SPEED for the speed and
CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
......@@ -3191,9 +3191,9 @@ FIT uImage format:
CONFIG_TPL_PAD_TO
Image offset to which the TPL should be padded before appending
the TPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
Modem Support:
--------------
......
......@@ -17,7 +17,7 @@ endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9 -msoft-float
-fno-common -ffixed-r9 -msoft-float
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
......
......@@ -31,10 +31,10 @@
/* reconfigure L2 cache aux control reg */
ldr r0, =0xC0 | /* tag RAM */ \
0x4 | /* data RAM */ \
1 << 24 | /* disable write allocate delay */ \
1 << 23 | /* disable write allocate combine */ \
1 << 22 /* disable write allocate */
0x4 | /* data RAM */ \
1 << 24 | /* disable write allocate delay */ \
1 << 23 | /* disable write allocate combine */ \
1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
ldr r3, [r4, #ROM_SI_REV]
......@@ -290,20 +290,20 @@ setup_pll_func:
setup_pll PLL1_BASE_ADDR, 800
setup_pll PLL3_BASE_ADDR, 400
setup_pll PLL3_BASE_ADDR, 400
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
cmp r1, #0x0
bne 1b
setup_pll PLL2_BASE_ADDR, 400
setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
......@@ -324,7 +324,7 @@ setup_pll_func:
cmp r1, #0x0
bne 1b
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL4_BASE_ADDR, 455
......@@ -358,13 +358,13 @@ setup_pll_func:
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#endif /* CONFIG_MX53 */
.endm
......
......@@ -140,7 +140,7 @@
reg = <0x12d40000 0x30>;
clock-frequency = <50000000>;
interrupts = <0 70 0>;
};
};
spi@131a0000 {
#address-cells = <1>;
......
......@@ -66,9 +66,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
mov pc, lr
mov pc, lr
#else
bx lr
bx lr
#endif
ENDPROC(relocate_code)
......@@ -261,7 +261,7 @@ static void decode_address(char *buf, unsigned long address)
if (!address)
sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
else if (address >= CONFIG_SYS_MONITOR_BASE &&
address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
else
sprintf(buf, "<0x%p> /* unknown address */", paddr);
......
......@@ -16,7 +16,7 @@ typedef struct SESR_args {
unsigned long ulMessageSize; /* message length in bytes */
unsigned long ulSFEntryPoint; /* entry point of secure function */
unsigned long ulMessagePtr; /* pointer to the buffer containing
the digital signature and message */
the digital signature and message */
unsigned long ulReserved1; /* reserved */
unsigned long ulReserved2; /* reserved */
} tSESR_args;
......
......@@ -20,7 +20,7 @@ extern void _int_handler(void);
static void show_frame(struct pt_regs *fp)
{
printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2,
fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8));
fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8));
printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp);
printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n",
fp->d0, fp->d1, fp->d2, fp->d3);
......
......@@ -475,7 +475,7 @@ void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char * const argv[])
printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n",
stat,
(stat & EPCS_STATUS_WIP) ? 1 : 0,
(stat & EPCS_STATUS_WEL) ? 1 : 0,
(stat & EPCS_STATUS_WEL) ? 1 : 0,
(stat & dev->prot_mask) ? "on" : "off" );
/* Configuration */
......
......@@ -548,7 +548,7 @@ __mulsi3 (SItype a, SItype b)
while (cnt)
{
if (cnt & 1)
{
{
res += b;
}
b <<= 1;
......
......@@ -138,8 +138,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* Code the jump to __reset here as the compiler is prone to
emitting a bad jump instruction if the function is in flash */
__asm__("l.movhi r1,hi(__reset); \
l.ori r1,r1,lo(__reset); \
l.jr r1");
l.ori r1,r1,lo(__reset); \
l.jr r1");
/* not reached, __reset does not return */
return 0;
}
......@@ -425,15 +425,15 @@ static int print_83xx_arb_event(int force)
};
int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
>> AEATR_EVENT_SHIFT;
>> AEATR_EVENT_SHIFT;
int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
>> AEATR_MSTR_ID_SHIFT;
>> AEATR_MSTR_ID_SHIFT;
int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
>> AEATR_TBST_SHIFT;
>> AEATR_TBST_SHIFT;
int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
>> AEATR_TSIZE_SHIFT;
>> AEATR_TSIZE_SHIFT;
int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
>> AEATR_TTYPE_SHIFT;
>> AEATR_TTYPE_SHIFT;
if (!force && !gd->arch.arbiter_event_address)
return 0;
......
......@@ -67,7 +67,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
pci_ctrl->pibar1 = 0;
pci_ctrl->piebar1 = 0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
i = hose->region_count++;
hose->regions[i].bus_start = 0;
......@@ -79,7 +79,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
hose->last_busno = 0xff;
pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
pci_register_hose(hose);
......
......@@ -143,14 +143,14 @@ void pci_405gp_init(struct pci_controller *hose)
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
}
ptmla_str = getenv("ptm2la");
ptmms_str = getenv("ptm2ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
}
#endif
......
......@@ -50,7 +50,7 @@ TFTP from server 192.168.1.1; our IP address is 192.168.20.71
Filename '/tftpboot/ipam390/u-boot.ais'.
Load address: 0xc0000000
Loading: ##################################
1.5 MiB/s
1.5 MiB/s
done
Bytes transferred = 493716 (78894 hex)
......
......@@ -87,10 +87,10 @@ static inline void __sevenseg_set (unsigned int value)
#if (SEVENSEG_ACTIVE == 0)
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| ((~value) & (~SEVENDEG_MASK_DP));
| ((~value) & (~SEVENDEG_MASK_DP));
#else
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| (value);
| (value);
#endif
piop->data = sevenseg_portval;
......
......@@ -6,39 +6,39 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk
if sf probe || sf probe || \
sf probe 1 27000000 || sf probe 1 27000000 ; then
echo "probed SPI ROM" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
echo "------- U-Boot versions match" ;
else
echo "Need U-Boot upgrade" ;
echo "Program in 5 seconds" ;
for n in 5 4 3 2 1 ; do
echo $n ;
sleep 1 ;
done
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
echo "------- U-Boot versions match" ;
else
echo "Need U-Boot upgrade" ;
echo "Program in 5 seconds" ;
for n in 5 4 3 2 1 ; do
echo $n ;
sleep 1 ;
done
echo "erasing" ;
sf erase 0 0x50000 ;
sf erase 0 0x50000 ;
# two steps to prevent bricking
echo "programming" ;
sf write 0x12000000 $offset $filesize ;
sf write 0x12000000 $offset $filesize ;
echo "verifying" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
while echo "---- U-Boot upgraded. reset" ; do
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
while echo "---- U-Boot upgraded. reset" ; do
sleep 120
done
else
echo "Read verification error" ;
fi
else
echo "Error re-reading EEPROM" ;
fi
fi
else
echo "Error reading boot loader from EEPROM" ;
fi
else
echo "Read verification error" ;
fi
else
echo "Error re-reading EEPROM" ;
fi
fi
else
echo "Error reading boot loader from EEPROM" ;
fi
else
echo "Error initializing EEPROM" ;
echo "Error initializing EEPROM" ;
fi ;
else
echo "No U-Boot image found on SD card" ;
......
......@@ -3,8 +3,8 @@
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
model = "Google Alex";
compatible = "google,alex", "intel,atom-pineview";
......@@ -12,13 +12,13 @@
silent_console = <0>;
};
gpio: gpio {};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
};
......@@ -3,8 +3,8 @@
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
......@@ -12,15 +12,15 @@
silent_console = <0>;
};
gpio: gpio {};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
spi {
#address-cells = <1>;
......
#
# GDB Init script for the Coldfire 5272 processor.
#
# The main purpose of this script is to configure the
# The main purpose of this script is to configure the
# DRAM controller so code can be loaded.
#
# This file was changed to suite the senTec COBRA5272 board.
#
#
define addresses
......
......@@ -487,7 +487,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last)
if (haderr > 0) {
printf (" failed\n");
rcode = 1;
rcode = 1;
}
else
printf (" done\n");
......
......@@ -47,7 +47,7 @@ else
echo no kernel to boot from $flash_krl, need tftp
fi
# Have a rootfs in flash?
# Have a rootfs in flash?
echo test for SQUASHfs at $flash_rfs
if imi $flash_rfs
......@@ -69,7 +69,7 @@ fi
# TFTP down a kernel
if printenv bootfile
then
then
tftp $tftp_addr $bootfile
setenv kernel $tftp_addr
echo I will boot the TFTP kernel
......@@ -90,7 +90,7 @@ if printenv rootpath
then
echo rootpath is $rootpath
if printenv initrd
then
then
echo initrd is also specified, so use $initrd
tftp $tftp2_addr $initrd
setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
......
......@@ -9,7 +9,7 @@
* Neutralize little endians.
*/
#define SWAP_LONG(data) ((unsigned long) \
(((unsigned long)(data) >> 24) | \
(((unsigned long)(data) >> 24) | \
((unsigned long)(data) << 24) | \
(((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
(((unsigned long)(data) << 8) & 0x00ff0000 )))
......
......@@ -43,7 +43,7 @@ int ide_preinit (void)
if (devbusfn != -1) {
cpci_hd_type = 1;
} else {
devbusfn = pci_find_device (0x1095, 0x3114, 0);
devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
cpci_hd_type = 2;
}
......
......@@ -746,7 +746,7 @@ static int gt_read_config_dword (struct pci_controller *hose,
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev));
} else {
......
......@@ -323,7 +323,7 @@ int flash_erase (flash_info_t *flash, int s_first, int s_last)
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
prot);
else
printf ("\n");
......@@ -365,7 +365,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_1MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
ERASEINFO(0x08000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x04000,1)
}
......@@ -376,7 +376,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_2MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
ERASEINFO(0x08000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x04000,1)
}
......@@ -387,7 +387,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_2MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x02000,2),
ERASEINFO(0x08000,1),
ERASEINFO(0x10000,31)
}
......@@ -398,7 +398,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_4MiB,
NumEraseRegions: 2,
regions: {ERASEINFO(0x10000,63),
ERASEINFO(0x02000,8)
ERASEINFO(0x02000,8)
}
}, {
......@@ -408,7 +408,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_4MiB,
NumEraseRegions: 2,
regions: {ERASEINFO(0x02000,8),
ERASEINFO(0x10000,63)
ERASEINFO(0x10000,63)
}
}
};
......
......@@ -60,7 +60,7 @@ flash_init (void)
#define CONFIG_SYS_BOOT_FLASH_WIDTH 1
#endif
size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
&flash_info[0]);
&flash_info[0]);
#ifndef CONFIG_P3G4
printf("[");
......@@ -97,17 +97,17 @@ flash_init (void)
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
flash_get_info(CONFIG_ENV_ADDR));
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
flash_get_info(CONFIG_ENV_ADDR));
#endif
flash_size = size_b0 + size_b1;
......
......@@ -785,7 +785,7 @@ galmpsc_shutdown(int mpsc)
GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
SDMA_TX_ABORT | SDMA_RX_ABORT);
SDMA_TX_ABORT | SDMA_RX_ABORT);
/* shut down the MPSC */
GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
......@@ -797,7 +797,7 @@ galmpsc_shutdown(int mpsc)
/* shut down the sdma engines. */
/* reset config to default */
GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
0x000000fc);
0x000000fc);
udelay(100);
......
......@@ -434,7 +434,7 @@ static int _initsdram(uint base, uint noMbytes)
*/
memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
udelay(200);
/* Run 8 refresh cycles */
......@@ -567,7 +567,7 @@ static int initsdram(uint base, uint *noMbytes)
if(!_initsdram(base, m))
{
*noMbytes += m;
*noMbytes += m;
return 0;
}
else
......
......@@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 3, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
......
......@@ -23,14 +23,14 @@ Overview
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
......
......@@ -129,12 +129,12 @@ void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
......
......@@ -427,7 +427,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);
......@@ -439,7 +439,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);
......
......@@ -270,9 +270,9 @@ int misc_init_r (void)
for (i = 0; i < 64; i++) {