Commit 9879842c authored by Masahiro Yamada's avatar Masahiro Yamada

ARM: uniphier: drop DCC micro support card support

Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards.  It has been painful to maintain
both.  Having one of them is enough.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
parent 1386233d
......@@ -26,29 +26,14 @@ config MACH_PH1_SLD8
endchoice
choice
prompt "UniPhier Support Card select"
optional
config PFC_MICRO_SUPPORT_CARD
bool "Support card with PFC CPLD"
help
This option provides support for the expansion board with PFC
original address mapping.
Say Y to use the on-board UART, Ether, LED devices.
config DCC_MICRO_SUPPORT_CARD
bool "Support card with DCC CPLD"
config MICRO_SUPPORT_CARD
bool "Use Micro Support Card"
help
This option provides support for the expansion board with DCC-
arranged address mapping that is compatible with legacy UniPhier
reference boards.
This option provides support for the expansion board, available
on some UniPhier reference boards.
Say Y to use the on-board UART, Ether, LED devices.
endchoice
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
......
......@@ -29,8 +29,7 @@ endif
obj-y += timer.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
......
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -8,8 +7,7 @@
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if defined(CONFIG_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
......
......@@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
......
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}
......@@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
......
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
}
......@@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
early_pinctrl.o pll_spectrum.o umc_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
......
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* only address/data multiplex mode is supported */
/* XECS0 : boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
/* XECS1 : sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
/* XECS2 : peripherals */
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE2);
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/*
* SBCTRL0* does not need settings because PH1-sLD8 has no support for
* XECS0. The boot swap must be enabled to boot from the support card.
*/
if (boot_is_swapped()) {
/* XECS1 : boot memory if boot swap is on */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
}
/* XECS4 : sub memory */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
/* XECS5 : peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
/* base address regsiters */
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0900bfff, SBBASE1); /* dummy */
writel(0x0400bc01, SBBASE4); /* sub memory */
writel(0x0800bf01, SBBASE5); /* peripherals */
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
/* dummy read to assure write process */
readl(SG_PINCTRL(0));
}
......@@ -8,11 +8,9 @@
#include <linux/io.h>
#include <mach/board.h>
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
#define PFC_MICRO_SUPPORT_CARD_RESET \
#define MICRO_SUPPORT_CARD_RESET \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
#define PFC_MICRO_SUPPORT_CARD_REVISION \
#define MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
/*
* 0: reset deassert, 1: reset
......@@ -22,65 +20,22 @@
*/
void support_card_reset_deassert(void)
{
writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
writel(0, MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
writel(3, MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
revision = readl(MICRO_SUPPORT_CARD_REVISION);
printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
return 0;
}
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
#define DCC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
void support_card_reset_deassert(void)
{
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
void support_card_reset(void)
{
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
if (revision >= 0x67) {
printf("(DCC CPLD version 3.%d.%d)\n",
revision >> 4, revision & 0xf);
return 0;
} else {
printf("(DCC CPLD unknown version)\n");
return -1;
}
}
#endif
int check_support_card(void)
{
......@@ -146,28 +101,11 @@ static int mem_is_flash(const struct memory_bank *mem)
return ret;
}
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/* {address, size} */
static const struct memory_bank memory_banks_boot_swap_off[] = {
/* {address, size} */
static const struct memory_bank memory_banks[] = {
{0x02000000, 0x01f00000},
};
static const struct memory_bank memory_banks_boot_swap_on[] = {
{0x00000000, 0x01f00000},
};
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
static const struct memory_bank memory_banks_boot_swap_off[] = {
{0x04000000, 0x02000000},
};
static const struct memory_bank memory_banks_boot_swap_on[] = {
{0x00000000, 0x02000000},
{0x04000000, 0x02000000},
};
#endif
static const struct memory_bank
*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
......@@ -187,13 +125,8 @@ static void detect_num_flash_banks(void)
cfi_flash_num_flash_banks = 0;
if (boot_is_swapped()) {
memory_bank = memory_banks_boot_swap_on;
end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
} else {
memory_bank = memory_banks_boot_swap_off;
end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
}
memory_bank = memory_banks;
end = memory_bank + ARRAY_SIZE(memory_banks);
for (; memory_bank < end; memory_bank++) {
if (cfi_flash_num_flash_banks >=
......
......@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_MACH_PH1_LD4=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_HUSH_PARSER=y
......
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_HUSH_PARSER=y
......
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_MACH_PH1_SLD3=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
CONFIG_HUSH_PARSER=y
......
......@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_MACH_PH1_SLD8=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_HUSH_PARSER=y
......
......@@ -62,19 +62,10 @@
/*
* Support card address map
*/
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE 0x08000000
# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
#endif
#define CONFIG_SUPPORT_CARD_BASE 0x03f00000
#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
......@@ -140,7 +131,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
......
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