Commit 9973e3c6 authored by Becky Bruce's avatar Becky Bruce Committed by Wolfgang Denk

Change initdram() return type to phys_size_t

This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.
Signed-off-by: default avatarBecky Bruce <becky.bruce@freescale.com>
parent 391fd93a
......@@ -39,7 +39,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int size,i;
......
......@@ -35,7 +35,7 @@
** ------
** int board_early_init_f(void)
** int checkboard(void)
** long int initdram(int board_type)
** phys_size_t initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
** void reset_phy(void)
......@@ -179,7 +179,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -81,7 +81,7 @@ int checkboard (void)
return 0;
}
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
return articiaS_ram_init ();
}
......
......@@ -1728,7 +1728,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
......
......@@ -1737,7 +1737,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
......
......@@ -165,7 +165,7 @@ void rpxclassic_init (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -102,7 +102,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -104,7 +104,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -110,7 +110,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -38,7 +38,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
......
......@@ -65,7 +65,7 @@ static uint sdram_table[] = {
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
};
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
......
......@@ -112,7 +112,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
u32 msize = 0;
......
......@@ -131,7 +131,7 @@ void setupBat (ulong size)
mtspr (DBAT7U, batu);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong size;
......
......@@ -50,7 +50,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}
......
......@@ -54,7 +54,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}
......@@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}
......@@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}
......@@ -29,7 +29,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}
......@@ -59,7 +59,7 @@ static void cram_bcr_write(u32 wr_val)
}
#endif
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
......
......@@ -453,7 +453,7 @@ int checkboard(void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
......
......@@ -70,7 +70,7 @@ int checkboard(void)
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long int ret;
......
......@@ -205,7 +205,7 @@ u32 ddr_clktr(u32 default_val) {
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
* code.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return CFG_MBYTES_SDRAM << 20;
}
......
......@@ -104,7 +104,7 @@ int checkboard(void)
return (0);
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long dram_size = 0;
......
......@@ -201,7 +201,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long dram_size = 0;
......
......@@ -52,7 +52,7 @@ extern void denali_core_search_data_eye(void);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)
......
......@@ -78,10 +78,10 @@ int checkboard(void)
}
/*************************************************************************
* long int initdram
* phys_size_t initdram
*
************************************************************************/
long int initdram(int board)
phys_size_t initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}
......
......@@ -89,7 +89,7 @@ int checkboard(void)
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return spd_sdram();
}
......@@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
long int initdram(int board)
phys_size_t initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;
......
......@@ -133,7 +133,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
char *s = getenv ("dramsize");
......
......@@ -340,7 +340,7 @@ int misc_init_r(void)
return (0);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
......
......@@ -64,7 +64,7 @@ int board_early_init_f(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
......
......@@ -90,7 +90,7 @@ int board_early_init_f(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
......
......@@ -98,7 +98,7 @@ long int fixed_sdram (void)
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
long int
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
......
......@@ -83,7 +83,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
......
......@@ -59,7 +59,7 @@ typedef struct SBootInfo {
/* barcohydra.c */
int checkboard(void);
long int initdram(int board_type);
phys_size_t initdram(int board_type);
void pci_init_board(void);
void check_flash(void);
int write_flash(char *addr, char value);
......
......@@ -104,7 +104,7 @@ static void sdram_start (int hi_addr)
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
......@@ -205,7 +205,7 @@ long int initdram (int board_type)
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
......
......@@ -39,7 +39,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
......
......@@ -48,7 +48,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
printf("SDRAM attributes:\n");
......
......@@ -97,7 +97,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
}
#endif /* CONFIG_BFIN_IDE */
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
......
......@@ -39,7 +39,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
......
......@@ -51,7 +51,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return 64*1024*1024;
}
......
......@@ -108,7 +108,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -82,7 +82,7 @@ static void sdram_start (int hi_addr)
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
......@@ -185,7 +185,7 @@ long int initdram (int board_type)
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
......
......@@ -114,7 +114,7 @@ static mem_conf_t* get_mem_config(int board_type)
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
......
......@@ -62,7 +62,7 @@ int checkboard(void)
/*
* Get RAM size.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */
}
......
......@@ -32,7 +32,7 @@ int checkboard (void)
return 0;
};
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
......
......@@ -233,7 +233,7 @@ int misc_init_f (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#ifdef CONFIG_CMA111
return (32L * 1024L * 1024L);
......
......@@ -61,7 +61,7 @@ int checkboard(void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int m, row, col, bank, i, ref;
unsigned long start, end;
......
......@@ -273,7 +273,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
return (size);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
......
......@@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
return (size);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
......
......@@ -170,7 +170,7 @@ int misc_init_r (void)
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (L1_MEMSIZE);
}
......
......@@ -120,7 +120,7 @@ int checkboard(void)
* configured by initialization code
*
*/
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;
......
......@@ -88,7 +88,7 @@ int checkboard(void)
* configured by initialization code
*
*/
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;
......
......@@ -45,7 +45,7 @@ int checkboard (void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long size;
long new_bank0_end;
......
......@@ -203,7 +203,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;
......
......@@ -27,7 +27,7 @@
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
......
......@@ -52,7 +52,7 @@ int checkflash (void)
return (0);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;
......
......@@ -162,7 +162,7 @@ long int dram_size (int board_type)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}
......
......@@ -104,7 +104,7 @@ long int dram_size (int board_type)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}
......
......@@ -251,7 +251,7 @@ int misc_init_r (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
......
......@@ -32,7 +32,7 @@
* initialize SDRAM/DDRAM controller.
* TBD: get data from I2C EEPROM
*****************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
......