Commit 9c6b47d5 authored by Matthew McClintock's avatar Matthew McClintock Committed by Andy Fleming

p1014rdb: set ddr bus width properly depending on SVR

Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image
Signed-off-by: default avatarMatthew McClintock <msm@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent be7bebea
......@@ -88,6 +88,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_16_BE 0x00100000
#define SDRAM_CFG_8_BE 0x00040000
......
......@@ -35,6 +35,7 @@ unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
u32 svr = mfspr(SPRN_SVR);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
......@@ -70,6 +71,16 @@ void sdram_init(void)
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
/* P1014 and it's derivatives support max 16bit DDR width */
if (svr == SVR_P1014) {
__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
/* For CS0_BNDS we divide the start and end address by 2, so we can just
* shift the entire register to achieve the desired result and the mask
* the value so we don't write reserved fields */
__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
}
/* mimic 500us delay, with busy isync() loop */
udelay(100);
......
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